decode.v

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

module decode(addr,addr_data,ALE_E,PSEN_N,reg_en,addr_match);
	input  [15:8]          addr;
	inout  [7:0]           addr_data;
	input  ALE_E;
	input  PSEN_N;
	output addr_match;
	//wire    addr_match;
	output [3:0]  reg_en;
	reg    [3:0]  reg_en;

	parameter BASE_ADDR   = 0;
	parameter STATUS_REG  = BASE_ADDR  + 8'h80;
	parameter CONTROL_REG = BASE_ADDR  + 8'h82;
	parameter DATAIN_REG  = BASE_ADDR  + 8'h84;
	parameter DATAOUT_REG = BASE_ADDR +  8'h86;
	  
	assign addr_match = (BASE_ADDR == addr) ? 1 : 0;
	always @(negedge ALE_E )
		case(addr_data)
			8'b10000000:				reg_en <= 1;
			8'b10000010:				reg_en <= 2; 
			8'b10000100:				reg_en <= 4;
			8'b10000110:        		reg_en <= 8;
			default:	        		reg_en <= 0;
		endcase
endmodule