cpld_bus.tan.qmsg

来自「CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Qua」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 156 11/29/2004 SJ Web Edition " "Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 04 20:04:40 2005 " "Info: Processing started: Thu Aug 04 20:04:40 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cpld_bus -c cpld_bus " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cpld_bus -c cpld_bus" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}