litenandfsm.vhdl

NAND Flash Controller & ECC VHDL Code

			else
				nextSTATE <= FetchERRORS;
			end if;		
		when FetchERRORS_waitforRE =>
			errlocADDRsel <= '1';
			MUXselIO := '0';
			hostIOdrv <= not(hostCE_L_tmp) and not(hostRE_L_tmp);
			hostIOout <= ErrorLOCations;

			incCOUNT <= not(intRE_L);
			if(hostCLE_H_tmp = '1' or hostALE_H_tmp = '1' or
				hostWE_L_tmp = '0' or (internal_COUNT = x"007" and intRE_L = '1')) then
				nextSTATE <= Start;
			else
				--if(hostCE_L_tmp = '0' and hostRE_L_tmp = '0') then
				--	nextSTATE <= FetchERRORSread;
				--else
				--	nextSTATE <= FetchERRORS_waitforRE;
				--end if;
				nextSTATE <= FetchERRORS_waitforRE;
			end if;
		--when FetchERRORSread => 
		--	errlocADDRsel <= '1';
		--	MUXselIO := '0';
		--	hostIOdrv <= '1';
		--	hostIOout <= ErrorLOCations;
		
		--	incCOUNT <= intRE_L;

		--	if(hostCLE_H_tmp = '1' or hostALE_H_tmp = '1' or
		--		hostWE_L_tmp = '0') then
		--		nextSTATE <= Start;
		--	else
		--		if(intRE_L = '1') then
		--			nextSTATE <= FetchERRORS_waitforRE;
		--		else
		--			nextSTATE <= FetchERRORSread;
		--		end if;
		--	end if;

-------------------- Read States --------------------------
		when ReadNAND =>
			
			nandIOtempVAL <= intIO;
			MUXselIO := '1';
			ResetECCgen <= '0';
			if(hostRB_L_tmp = '0') then
				nextSTATE <= ReadNANDwaitforRB;
			else
				nextSTATE <= ReadNAND;
			end if;
			STATEvec <= "0010";
			--STATEvec <= intRB_L & "010";
		when ReadNANDwaitforRB =>
			nandIOtempVAL <= x"FF";
			MUXselIO := '1';
			if(hostRB_L_tmp = '1' and hostRE_L_tmp = '0') then
				nextSTATE <= ReadECCcalc;
			else
				nextSTATE <= ReadNANDwaitforRB;
			end if;
			HammingINmuxSEL <= '1';
			STATEvec <= "0011";
		when ReadECCcalc =>
			hostIOdrv <= '1';
			hostIOout <= nandIO;
			-- pipe the inputs to the outputs
			MUXselIO := '1';
			-- ECC state machine control
			nandIOtempVAL <= x"CC";

			if (internal_COUNT <= x"7FF" or internal_COUNT = x"FFF") then
				SHOOTenable <= intRE_L;
			else
				SHOOTenable <= '1';
			end if;
			-- Increment Counter
			--incCOUNT <= not(intRE_L);
			incCOUNT <= not(hostRE_L_tmp);
		
			if (Done2100Bytes = '1' and intRE_L = '1') then
				nextSTATE <= ReadECCfromNAND;
			else
				nextSTATE <= ReadECCcalc;
			end if;
			HammingINmuxSEL <= '1';
			STATEvec <= "0100";
		when ReadECCfromNAND =>
			MUXselIO := '0';
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmRE_L := TUGthelines;
			hostIOdrv <= '0';
			-- 1 as we do not want to write to the lines
			--nandDriveBuffer <= '1';
			-- Increment Counter
			if(cntTUG = "100") then
				incCOUNT <= '1';
			else
				incCOUNT <= '0';
			end if;

			ResetTUGthelines <= '1';
			if (internal_COUNT >= x"83F") then
				nextSTATE <= ThrowINT;
			else
				nextSTATE <= ReadECCfromNAND;
			end if;
			STATEvec <= "0101";
		when ThrowINT =>
			MUXselIO := '1';
			interrINT_H <= NeedINT;
			nextSTATE <= Start;
			STATEvec <= "1100";
----------------------- Program NAND states -------------------------
		when ProgramNAND =>
			MUXselIO := '1';
			if(hostALE_H_tmp = '1') then
				nextSTATE <= ProgramNANDaddr;
			else
				nextSTATE <= ProgramNAND;
			end if;
			STATEvec <= "0110";
		when ProgramNANDaddr =>
			MUXselIO := '1';
			ResetECCgen <= '0';
			incCOUNT <= not(intWE_L);
			if(hostALE_H_tmp = '0' and internal_COUNT >= x"004" and
				not(internal_COUNT = x"FFF")) then
				nextSTATE <= ProgramNANDbufST2;
			else
				nextSTATE <= ProgramNANDaddr;
			end if;
			STATEvec <= "0111";

		when ProgramNANDbufST2 =>
			MUXselIO := '1';
			nextSTATE <= ProgramNANDeccCALC;
			ResetCOUNTER_L <= '0';
			STATEvec <= "0111";

		when ProgramNANDeccCALC =>
			-- pipe the inputs to the outputs
			MUXselIO := '1';
			
			-- ECC state machine control
			--ResetECCgen <= '1';
			if (internal_COUNT <= x"7FF" or internal_COUNT = x"FFF") then
				SHOOTenable <= intWE_L;
			else
				SHOOTenable <= '1';
			end if;
			-- Increment Counter
			--incCOUNT <= not(intWE_L);
			incCOUNT <= not(hostWE_L_tmp);

			-- internal_COUNT >= x"834" and 
			if ( (Done2100Bytes = '1' and intWE_L = '1') or (hostCLE_H_tmp = '1' and hostCE_L_tmp = '0'
					and hostWE_L_tmp = '0' and hostIOin_tmp = x"10") ) then
				nextSTATE <= ProgramNANDbufST0;
			else
				nextSTATE <= ProgramNANDeccCALC;
			end if;
			STATEvec <= "1000";
		when ProgramNANDbufST0 =>
			MUXselIO := '0';
			-- pipe the inputs to the outputs
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmWE_L := '1';

			FFintIO <= '1';
			if (internal_COUNT >= x"833") then
				nextSTATE <= ProgramNANDbufST1;
			else
				nextSTATE <= ProgramNANDfillinOther;
			end if;

		when ProgramNANDfillinOther =>
			MUXselIO := '0';
			-- pipe the inputs to the outputs
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmWE_L := TUGthelines;
					
			if(cntTUG = "100") then
				incCOUNT <= '1';
			else
				incCOUNT <= '0';
			end if;
			ResetTUGthelines <= '1';

			-- fire x"FF" into the intIO register
			FFintIO <= '1';
			if (internal_COUNT >= x"833") then
				nextSTATE <= ProgramNANDbufST1;
			else
				nextSTATE <= ProgramNANDfillinOther;
			end if;
		when ProgramNANDbufST1 =>
			MUXselIO := '0';
			-- pipe the inputs to the outputs
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmWE_L := '1';

			nextSTATE <= ProgramNANDeccwrite;
			ECCgenCNTsel <= '1';

		when ProgramNANDeccwrite =>
			ECCgenCNTsel <= '1';
			nandIOtempVAL <= HAMMING8bitin;

			MUXselIO := '0';
			-- pipe the inputs to the outputs
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmWE_L := TUGthelines;

			-- Increment Counter
			if(cntTUG = "100") then
				incCOUNT <= '1';
			else
				incCOUNT <= '0';
			end if;
			ResetTUGthelines <= '1';

			-- These 2 make sure the hamming is written
			-- to the NAND lines
			if (internal_COUNT >= x"83F") then
				nextSTATE <= ProgramNANDbufST3;
			else
				nextSTATE <= ProgramNANDeccwrite;
			end if;
			-- 1 as we do not want to write to the lines
			--nandDriveBuffer <= '0';
			STATEvec <= "1001";

		when ProgramNANDbufST3 =>
			MUXselIO := '0';
			-- pipe the inputs to the outputs
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmWE_L := '1';
			ResetTUGthelines <= '0';
			SELintIO10 <= '1';

			nextSTATE <= ProgramNANDcmd10h;
		when ProgramNANDcmd10h => -- this state writes the command
			MUXselIO := '0';
			fsmCE_L := '0';
			fsmRB_L := '0';
			fsmCLE_H := '1';
			fsmWE_L := TUGthelines;

			SELintIO10 <= '1';
			ResetTUGthelines <= '1';
			if(cntTUG = "100") then
				incCOUNT <= '1';
			else
				incCOUNT <= '0';
			end if;
			STATEvec <= "1010";
			if(internal_COUNT >= x"840") then
				nextSTATE <= Start;
			else
				nextSTATE <= ProgramNANDcmd10h;
			end if;
						
		when others =>
			MUXselIO := '0';
			nextSTATE <= Start;
			STATEvec <= "1011";
	end case;
	if(enableECCmodule = '0') then
		hostRB_L <= nandRB_L;
		nandCE_L <= hostCE_L;
		nandCLE_H <= hostCLE_H;
		nandALE_H <= hostALE_H;
		nandWE_L <= hostWE_L;
		nandRE_L <= hostRE_L;
		nandWP_L <= hostWP_L;
	elsif (MUXselIO = '0') then

		hostRB_L <= fsmRB_L;
		nandCE_L <= fsmCE_L;
		nandCLE_H <= fsmCLE_H;
		nandALE_H <= fsmALE_H;
		nandWE_L <= fsmWE_L;
		nandRE_L <= fsmRE_L;
		nandWP_L <= fsmWP_L;
	else
		hostRB_L <= intRB_L;
		nandCE_L <= intCE_L;
		nandCLE_H <= intCLE_H;
		nandALE_H <= intALE_H;
		nandWE_L <= intWE_L;
		nandRE_L <= intRE_L;
		nandWP_L <= intWP_L;
	end if;
end process COMBfsmOUTPUTS;

LATCHdata: process(clk, Reset_L, hostIOin, hostCE_L, hostCLE_H, hostALE_H,
				hostWE_L, hostRE_L, hostWP_L)
begin
	if(rising_edge(clk)) then
		if(Reset_L = '0') then
			intIO <= x"FF";
    			intCE_L <= '1';
			intCLE_H <= '0';
			intALE_H <= '0';
			intWE_L <= '1';
			intRE_L <= '1';
			intWP_L <= '1';
			intRB_L <= '1';
		else
			hostCE_L_tmp <= hostCE_L;
			hostCLE_H_tmp <= hostCLE_H;
			hostALE_H_tmp <= hostALE_H;
			hostWE_L_tmp <= hostWE_L;
			hostRE_L_tmp <= hostRE_L;
			hostWP_L_tmp <= hostWP_L;
			hostRB_L_tmp <= nandRB_L;
			
			hostIOin_tmp <= hostIOin;			
			--intIO <= hostIO;
			if(FFintIO = '1') then
				intIO <= x"FF";
			else
				if(SELintIO10 = '1') then
					intIO <= x"10";
				else
					intIO <= hostIOin_tmp;
				end if;
			end if;
    			intCE_L <= hostCE_L_tmp;
			intCLE_H <= hostCLE_H_tmp;
			intALE_H <= hostALE_H_tmp;
			intWE_L <= hostWE_L_tmp;
			intRE_L <= hostRE_L_tmp;
			intWP_L <= hostWP_L_tmp;
			intRB_L <= hostRB_L_tmp;
		end if;
	end if;
end process LATCHdata;

REorREdelayed: process(intRE_L, clk, Reset_L, firstVAL)
begin
	if(rising_edge(clk)) then
		if(Reset_L = '0') then
			firstVAL <= '0';
			--secondVAL <= '0';
		else
			firstVAL <= intRE_L;
			--secondVAL <= firstVAL;
		end if;
	end if;
	-- REstatus <= not(intRE_L) or secondVAL or firstVAL;
	--ONEdelayedRE <= not(intRE_L);
end process REorREdelayed;

--ONEdelayedRE <= not(intRE_L);

BUScontend: process(nandIO, intIO, HammingINmuxSEL, triSTATEnandIO, 
				nandIOtempVAL)
begin
	if (HammingINmuxSEL = '1') then
		dataFORecc <= nandIO;
	else
		dataFORecc <= intIO;
	end if;
	if(triSTATEnandIO = '0') then
		nandIO <= nandIOtempVAL;
	else
		nandIO <= "ZZZZZZZZ";
	end if;

end process BUScontend;

--DEBUGvector <= whtHOSTio & REstatus & HAMMINGtoNANDsel & '0';
--DEBUGvector <= triSTATEnandIO & nandIOtempVAL(2 downto 0);
DEBUGvector <= errlocADDRsel & internal_COUNT(2 downto 0);
end syn;