iolpc2104.h

LPC2106开发板上面的uCOS移植代码最新版2.83

/***************************************************************************
 **                        
 **    This file defines the Special Function Registers for
 **    Philips LPC2104
 **    
 **    Used with ICCARM and AARM.
 **                                
 **    (c) Copyright IAR Systems 2003
 **                                
 **    $Revision: 1.2 $
 **                                
 **    Note: Only little endian addressing of 8 bit registers.
 ***************************************************************************/

#ifndef __IOLPC2104_H
#define __IOLPC2104_H


#if (((__TID__ >> 8) & 0x7F) != 0x4F)     /* 0x4F = 79 dec */
#error This file should only be compiled by ICCARM/AARM
#endif


#include "io_macros.h"

/***************************************************************************
 ***************************************************************************
 **                            
 **    IOLPC210X SPECIAL FUNCTION REGISTERS
 **                            
 ***************************************************************************
 ***************************************************************************
 ***************************************************************************/

/* C specific declarations  ************************************************/

#ifdef __IAR_SYSTEMS_ICC__

#ifndef _SYSTEM_BUILD
  #pragma system_include
#endif

/* VIC Interrupt registers */
typedef struct {
  __REG32 INT0            :1;
  __REG32 INT1            :1;
  __REG32 INT2            :1;
  __REG32 INT3            :1;
  __REG32 INT4            :1;
  __REG32 INT5            :1;
  __REG32 INT6            :1;
  __REG32 INT7            :1;
  __REG32 INT8            :1;
  __REG32 INT9            :1;
  __REG32 INT10           :1;
  __REG32 INT11           :1;
  __REG32 INT12           :1;
  __REG32 INT13           :1;
  __REG32 INT14           :1;
  __REG32 INT15           :1;
  __REG32 INT16           :1;
  __REG32 INT17           :1;
  __REG32 INT18           :1;
  __REG32 INT19           :1;
  __REG32 INT20           :1;
  __REG32 INT21           :1;
  __REG32 INT22           :1;
  __REG32 INT23           :1;
  __REG32 INT24           :1;
  __REG32 INT25           :1;
  __REG32 INT26           :1;
  __REG32 INT27           :1;
  __REG32 INT28           :1;
  __REG32 INT29           :1;
  __REG32 INT30           :1;
  __REG32 INT31           :1;
} __vicint_bits;

/* VIC Vector control registers */
typedef struct {
  __REG32 NUMBER          :5;
  __REG32 ENABLED         :1;
  __REG32                 :26;
} __vicvectcntl_bits;

/* VIC protection enable register */
typedef struct {
  __REG32 PROTECT         :1;
  __REG32                 :31;
} __vicprotection_bits;



/* Pin function select register 0 */
typedef struct {
  __REG32 P0_0            :2;
  __REG32 P0_1            :2;
  __REG32 P0_2            :2;
  __REG32 P0_3            :2;
  __REG32 P0_4            :2;
  __REG32 P0_5            :2;
  __REG32 P0_6            :2;
  __REG32 P0_7            :2;
  __REG32 P0_8            :2;
  __REG32 P0_9            :2;
  __REG32 P0_10           :2;
  __REG32 P0_11           :2;
  __REG32 P0_12           :2;
  __REG32 P0_13           :2;
  __REG32 P0_14           :2;
  __REG32 P0_15           :2;
} __pinsel0_bits;

/* Pin function select register 1 */
typedef struct {
  __REG32 P0_16           :2;
  __REG32 P0_17           :2;
  __REG32 P0_18           :2;
  __REG32 P0_19           :2;
  __REG32 P0_20           :2;
  __REG32 P0_21           :2;
  __REG32 P0_22           :2;
  __REG32 P0_23           :2;
  __REG32 P0_24           :2;
  __REG32 P0_25           :2;
  __REG32 P0_26           :2;
  __REG32 P0_27           :2;
  __REG32 P0_28           :2;
  __REG32 P0_29           :2;
  __REG32 P0_30           :2;
  __REG32 P0_31           :2;
} __pinsel1_bits;


/* GPIO registers */
typedef struct {
  __REG32 P0_0            :1;
  __REG32 P0_1            :1;
  __REG32 P0_2            :1;
  __REG32 P0_3            :1;
  __REG32 P0_4            :1;
  __REG32 P0_5            :1;
  __REG32 P0_6            :1;
  __REG32 P0_7            :1;
  __REG32 P0_8            :1;
  __REG32 P0_9            :1;
  __REG32 P0_10           :1;
  __REG32 P0_11           :1;
  __REG32 P0_12           :1;
  __REG32 P0_13           :1;
  __REG32 P0_14           :1;
  __REG32 P0_15           :1;
  __REG32 P0_16           :1;
  __REG32 P0_17           :1;
  __REG32 P0_18           :1;
  __REG32 P0_19           :1;
  __REG32 P0_20           :1;
  __REG32 P0_21           :1;
  __REG32 P0_22           :1;
  __REG32 P0_23           :1;
  __REG32 P0_24           :1;
  __REG32 P0_25           :1;
  __REG32 P0_26           :1;
  __REG32 P0_27           :1;
  __REG32 P0_28           :1;
  __REG32 P0_29           :1;
  __REG32 P0_30           :1;
  __REG32 P0_31           :1;
} __gpio_bits;


/* UART interrupt enable register */
typedef struct {
  __REG8 RDAIE            :1;
  __REG8 THREIE           :1;
  __REG8 RXLSIE           :1;
  __REG8                  :5;
} __uartier0_bits;


/* UART interrupt enable register */
typedef struct {
  __REG8 RDAIE            :1;
  __REG8 THREIE           :1;
  __REG8 RXLSIE           :1;
  __REG8 MSIE             :1;
  __REG8                  :4;
} __uartier1_bits;


/* UART interrupt identification register and fifo control register */
typedef union {
  /* UxIIR */
  struct {
    __REG8 IP             :1;
    __REG8 IID            :3;
    __REG8                :2;
    __REG8 IIRFE          :2;
  };
  /* UxFCR */
  struct {
    __REG8 FCRFE          :1;
    __REG8 RFR            :1;
    __REG8 TFR            :1;
    __REG8                :3;
    __REG8 RTLS           :2;
  };
} __uartfcriir_bits;

/* UART line control register */
typedef struct {
  __REG8 WLS              :2;
  __REG8 SBS              :1;
  __REG8 PE               :1;
  __REG8 PS               :2;
  __REG8 BC               :1;
  __REG8 DLAB             :1;
} __uartlcr_bits;

/* UART modem control register */
typedef struct {
  __REG8 DTR              :1;
  __REG8 RTS              :1;
  __REG8                  :2;
  __REG8 LMS              :1;
  __REG8                  :3;
} __uartmcr_bits;

/* UART line status register */
typedef struct {
  __REG8 DR               :1;
  __REG8 OE               :1;
  __REG8 PE               :1;
  __REG8 FE               :1;
  __REG8 BI               :1;
  __REG8 THRE             :1;
  __REG8 TEMT             :1;
  __REG8 RXFE             :1;
} __uartlsr_bits;

/* UART modem status register */
typedef union {
  //U1MSR
  struct {
  __REG8 DCTS             :1;
  __REG8 DDSR             :1;
  __REG8 TERI             :1;
  __REG8 DDCD             :1;
  __REG8 CTS              :1;
  __REG8 DSR              :1;
  __REG8 RI               :1;
  __REG8 DCD              :1;
  };
  //U1MSR
  struct {
  __REG8 MSR0             :1;
  __REG8 MSR1             :1;
  __REG8 MSR2             :1;
  __REG8 MSR3             :1;
  __REG8 MSR4             :1;
  __REG8 MSR5             :1;
  __REG8 MSR6             :1;
  __REG8 MSR7             :1;
  };
} __uartmsr_bits;


/* I2C control set register */
typedef struct {
  __REG32                 :2;
  __REG32 AA              :1;
  __REG32 SI              :1;
  __REG32 STO             :1;
  __REG32 STA             :1;
  __REG32 I2EN            :1;
  __REG32                 :25;
} __i2conset_bits;

/* I2C control clear register */
typedef struct {
  __REG32                 :2;
  __REG32 AAC             :1;
  __REG32 SIC             :1;
  __REG32                 :1;
  __REG32 STAC            :1;
  __REG32 I2ENC           :1;
  __REG32                 :25;
} __i2conclr_bits;

/* I2C status register */
typedef struct {
  __REG32 STATUS          :8;
  __REG32                 :24;
} __i2stat_bits;

/* I2C data register */
typedef struct {
  __REG32 DATA            :8;
  __REG32                 :24;
} __i2dat_bits;

/* I2C slave address register */
typedef struct {
  __REG32 GC              :1;
  __REG32 ADDR            :7;
  __REG32                 :24;
} __i2adr_bits;

/* I2C scl duty cycle register */
typedef struct {
  __REG32 COUNT           :16;
  __REG32                 :16;
} __i2scl_bits;


/* SPI control register */
typedef struct {
  __REG32                 :3;
  __REG32 CPHA            :1;
  __REG32 CPOL            :1;
  __REG32 MSTR            :1;
  __REG32 LSBF            :1;
  __REG32 SPIE            :1;
  __REG32                 :24;
} __spcr_bits;

/* SPI status register */
typedef struct {
  __REG32                 :3;
  __REG32 ABRT            :1;
  __REG32 MODF            :1;
  __REG32 ROVR            :1;
  __REG32 WCOL            :1;
  __REG32 SPIF            :1;
  __REG32                 :24;
} __spsr_bits;

/* SPI data register */
typedef struct {
  __REG32 DATA            :8;
  __REG32                 :24;
} __spdr_bits;

/* SPI clock counter register */
typedef struct {
  __REG32 COUNTER         :8;
  __REG32                 :24;
} __spccr_bits;

/* SPI interrupt register */
typedef struct {
  __REG32 SPIINT          :1;
  __REG32                 :31;
} __spint_bits;



/* TIMER interrupt register */
typedef struct {
  __REG32 MR0INT          :1;
  __REG32 MR1INT          :1;
  __REG32 MR2INT          :1;
  __REG32 MR3INT          :1;
  __REG32 CR0INT          :1;
  __REG32 CR1INT          :1;
  __REG32 CR2INT          :1;
  __REG32 CR3INT          :1;
  __REG32                 :24;