i860.md

这是一个linux 嵌入式系统中很重要的GCC编译器程序

    {
      CC_STATUS_INIT;
      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
      cc_status.mdep = XEXP (operands[1], 0);
      return \"orh %h1,%?r0,%?r31\;ld.s %L1(%?r31),%0\";
    }
  else
    return \"ld.s %1,%0\";
}")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(sign_extend:HI
	 (match_operand:QI 1 "nonimmediate_operand" "mr")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"shl 24,%1,%0\;shra 24,%0,%0\";
  if (GET_CODE (operands[1]) == CONST_INT)
    abort ();
  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    {
      CC_STATUS_INIT;
      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
      cc_status.mdep = XEXP (operands[1], 0);
      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
    }
  else
    return \"ld.b %1,%0\";
}")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:QI 1 "nonimmediate_operand" "mr")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"shl 24,%1,%0\;shra 24,%0,%0\";
  if (GET_CODE (operands[1]) == CONST_INT)
    abort ();
  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    {
      CC_STATUS_INIT;
      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
      cc_status.mdep = XEXP (operands[1], 0);
      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
    }
  else
    return \"ld.b %1,%0\";
}")

;; Signed bitfield extractions come out looking like
;;	(shiftrt (sign_extend (shift <Y> <C1>)) <C2>)
;; which we expand poorly as four shift insns.
;; These patterns yield two shifts:
;;	(shiftrt (shift <Y> <C3>) <C4>)
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI
	 (sign_extend:SI
	  (match_operand:QI 1 "register_operand" "r"))
	 (match_operand:SI 2 "logic_int" "n")))]
  "INTVAL (operands[2]) < 8"
  "*
{
  return \"shl 24,%1,%0\;shra 24+%2,%0,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI
	 (sign_extend:SI
	  (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r")
				(match_operand:SI 2 "logic_int" "n")) 0))
	 (match_operand:SI 3 "logic_int" "n")))]
  "INTVAL (operands[3]) < 8"
  "*
{
  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI
	 (sign_extend:SI
	  (ashift:QI (match_operand:QI 1 "register_operand" "r")
		     (match_operand:QI 2 "logic_int" "n")))
	 (match_operand:SI 3 "logic_int" "n")))]
  "INTVAL (operands[3]) < 8"
  "*
{
  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
}")

;; Special patterns for optimizing bit-field instructions.

;; First two patterns are for bitfields that came from memory
;; testing only the high bit.  They work with old combiner.

(define_insn ""
  [(set (cc0)
	(eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
						    (const_int 7)) 0))
	    (const_int 0)))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"and 128,%0,%?r0\";
}")

(define_insn ""
  [(set (cc0)
	(eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
						    (const_int 7)) 0))
	    (const_int 0)))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"and 128,%0,%?r0\";
}")

;; next two patterns are good for bitfields coming from memory
;; (via pseudo-register) or from a register, though this optimization
;; is only good for values contained wholly within the bottom 13 bits
(define_insn ""
  [(set (cc0)
	(eq 
	 (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
			      (match_operand:SI 1 "logic_int" "n"))
		 (match_operand:SI 2 "logic_int" "n"))
	 (const_int 0)))]
  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
  "*
{
  CC_STATUS_PARTIAL_INIT;
  operands[2] = GEN_INT ((INTVAL (operands[2]) << INTVAL (operands[1])));
  return \"and %2,%0,%?r0\";
}")

(define_insn ""
  [(set (cc0)
	(eq 
	 (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
			      (match_operand:SI 1 "logic_int" "n"))
		 (match_operand:SI 2 "logic_int" "n"))
	 (const_int 0)))]
  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
  "*
{
  CC_STATUS_PARTIAL_INIT;
  operands[2] = GEN_INT ((INTVAL (operands[2]) << INTVAL (operands[1])));
  return \"and %2,%0,%?r0\";
}")

;; Conversions between float and double.

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(float_extend:DF
	 (match_operand:SF 1 "register_operand" "f")))]
  ""
  "fmov.sd %1,%0")

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(float_truncate:SF
	 (match_operand:DF 1 "register_operand" "f")))]
  ""
  "fmov.ds %1,%0")

;; Conversion between fixed point and floating point.
;; Note that among the fix-to-float insns
;; the ones that start with SImode come first.
;; That is so that an operand that is a CONST_INT
;; (and therefore lacks a specific machine mode).
;; will be recognized as SImode (which is always valid)
;; rather than as QImode or HImode.

;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general floatsisf2 pattern.
(define_expand "floatsidf2"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "")
			      (const_int -2147483648)))
   (set (match_dup 5) (match_dup 3))
   (set (subreg:SI (match_dup 5) 0) (match_dup 4))
   (set (match_operand:DF 0 "register_operand" "")
	(minus:DF (match_dup 5) (match_dup 2)))]
  ""
  "
{
  REAL_VALUE_TYPE d;
  /* 4503601774854144 is  (1 << 30) * ((1 << 22) + (1 << 1)).  */
  d = REAL_VALUE_ATOF (\"4503601774854144\", DFmode);
  operands[2] = gen_reg_rtx (DFmode);
  operands[3] = CONST_DOUBLE_FROM_REAL_VALUE (d, DFmode);
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = gen_reg_rtx (DFmode);
}")

;; Floating to fixed conversion.

(define_expand "fix_truncdfsi2"
  ;; This first insn produces a double-word value
  ;; in which only the low word is valid.
  [(set (match_dup 2)
	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
   (set (match_operand:SI 0 "register_operand" "=f")
	(subreg:SI (match_dup 2) 0))]
  ""
  "
{
  operands[2] = gen_reg_rtx (DImode);
}")

;; Recognize the first insn generated above.
;; This RTL looks like a fix_truncdfdi2 insn,
;; but we dont call it that, because only 32 bits
;; of the result are valid.
;; This pattern will work for the intended purposes 
;; as long as we do not have any fixdfdi2 or fix_truncdfdi2.
(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=f")
	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
  ""
  "ftrunc.dd %1,%0")

(define_expand "fix_truncsfsi2"
  ;; This first insn produces a double-word value
  ;; in which only the low word is valid.
  [(set (match_dup 2)
	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
   (set (match_operand:SI 0 "register_operand" "=f")
	(subreg:SI (match_dup 2) 0))]
  ""
  "
{
  operands[2] = gen_reg_rtx (DImode);
}")

;; Recognize the first insn generated above.
;; This RTL looks like a fix_truncsfdi2 insn,
;; but we dont call it that, because only 32 bits
;; of the result are valid.
;; This pattern will work for the intended purposes 
;; as long as we do not have any fixsfdi2 or fix_truncsfdi2.
(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=f")
	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
  ""
  "ftrunc.sd %1,%0")

;;- arithmetic instructions

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,*f")
	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f")
		 (match_operand:SI 2 "arith_operand" "rI,*f")))]
  ""
  "*
{
  if (which_alternative == 1)
    return \"fiadd.ss %2,%1,%0\";
  CC_STATUS_PARTIAL_INIT;
  return \"addu %2,%1,%0\";
}")

(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=f")
	(plus:DI (match_operand:DI 1 "register_operand" "%f")
		 (match_operand:DI 2 "register_operand" "f")))]
  ""
  "fiadd.dd %1,%2,%0")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,*f")
	(minus:SI (match_operand:SI 1 "register_operand" "r,I,*f")
		  (match_operand:SI 2 "arith_operand" "rI,r,*f")))]
  ""
  "*
{
  if (which_alternative == 2)
    return \"fisub.ss %1,%2,%0\";
  CC_STATUS_PARTIAL_INIT;
  if (REG_P (operands[2]))
    return \"subu %1,%2,%0\";
  operands[2] = GEN_INT (- INTVAL (operands[2]));
  return \"addu %2,%1,%0\";
}")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "register_operand" "=f")
	(minus:DI (match_operand:DI 1 "register_operand" "f")
		  (match_operand:DI 2 "register_operand" "f")))]
  ""
  "fisub.dd %1,%2,%0")

(define_expand "mulsi3"
  [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
   (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
   (clobber (match_dup 3))
   (set (subreg:SI (match_dup 3) 0)
	(mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
  ""
  "
{
  if (WORDS_BIG_ENDIAN)
    emit_insn (gen_mulsi3_big (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_mulsi3_little (operands[0], operands[1], operands[2]));
  DONE;
}")

(define_expand "mulsi3_little"
  [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
   (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
   (clobber (match_dup 3))
   (set (subreg:SI (match_dup 3) 0)
	(mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
  "! WORDS_BIG_ENDIAN"
  "
{
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DImode);
}")

(define_expand "mulsi3_big"
  [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" ""))
   (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" ""))
   (clobber (match_dup 3))
   (set (subreg:SI (match_dup 3) 1)
	(mult:SI (subreg:SI (match_dup 4) 1) (subreg:SI (match_dup 5) 1)))
   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 1))]
  "WORDS_BIG_ENDIAN"
  "
{
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DImode);
}")

(define_insn ""
  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0)
	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0)
		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))]
  "! WORDS_BIG_ENDIAN"
  "fmlow.dd %2,%1,%0")

(define_insn ""
  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 1)
	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 1)
		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 1)))]
  "WORDS_BIG_ENDIAN"
  "fmlow.dd %2,%1,%0")

;;- and instructions (with compliment also)			   
(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rL")))]
  ""
  "*
{
  rtx xop[3];

  CC_STATUS_PARTIAL_INIT;
  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
    return \"and %2,%1,%0\";
  if ((INTVAL (operands[2]) & 0xffff) == 0)
    {
      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
      return \"andh %2,%1,%0\";
    }
  xop[0] = operands[0];
  xop[1] = operands[1];
  xop[2] = GEN_INT (~INTVAL (operands[2]) & 0xffff);
  output_asm_insn (\"andnot %2,%1,%0\", xop);
  operands[2] = GEN_INT (~(unsigned) INTVAL (operands[2]) >> 16);
  return \"andnoth %2,%0,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (not:SI (match_operand:SI 1 "register_operand" "rn"))
		(match_operand:SI 2 "register_operand" "r")))]
  ""
  "*
{
  rtx xop[3];

  CC_STATUS_PARTIAL_INIT;
  if (REG_P (operands[1]) || LOGIC_INT (operands[1]))
    return \"andnot %1,%2,%0\";
  if ((INTVAL (operands[1]) & 0xffff) == 0)
    {
      operands[1] = GEN_INT ((unsigned) INTVAL (operands[1]) >> 16);
      return \"andnoth %1,%2,%0\";
    }
  xop[0] = operands[0];
  xop[1] = GEN_INT ((INTVAL (operands[1]) & 0xffff));
  xop[2] = operands[2];
  output_asm_insn (\"andnot %1,%2,%0\", xop);
  operands[1] = GEN_INT ((unsigned) INTVAL (operands[1]) >> 16);
  return \"andnoth %1,%0,%0\";
}")

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rL")))]
  ""
  "*
{
  rtx xop[3];

  CC_STATUS_PARTIAL_INIT;
  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
    return \"or %2,%1,%0\";
  if ((INTVAL (operands[2]) & 0xffff) == 0)
    {
      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
      return \"orh %2,%1,%0\";
    }
  xop[0] = operands[0];
  xop[1] = operands[1];
  xop[2] = GEN_INT ((INTVAL (operands[2]) & 0xffff));
  output_asm_insn (\"or %2,%1,%0\", xop);
  operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
  return \"orh %2,%0,%0\";
}")

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rL")))]
  ""
  "*
{
  rtx xop[3];

  CC_STATUS_PARTIAL_INIT;
  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
    return \"xor %2,%1,%0\";
  if ((INTVAL (operands[2]) & 0xffff) == 0)
    {
      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
      return \"xorh %2,%1,%0\";
    }
  xop[0] = operands[0];
  xop[1] = operands[1];
  xop[2] = GEN_INT ((INTVAL (operands[2]) & 0xffff));
  output_asm_insn (\"xor %2,%1,%0\", xop);
  operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
  return \"xorh %2,%0,%0\";