epp_and_sram.v

并口epp模式下与fpga通信例子

module EPP_and_SRAM(EPP_Write0,EPP_Data,EPP_Interrupt,EPP_Wait,EPP_DataStrobe0,EPP_Reset0,EPP_AddressStrobe0,
	SRAM_CE,SRAM_OE,SRAM_WE,SRAM_IO,SRAM_Addr,clk24,rst,led);

	//EPP interface signals
	input EPP_Write0;
	inout [7:0] EPP_Data;
	output EPP_Interrupt;
	output EPP_Wait;
	input EPP_DataStrobe0;
	input EPP_Reset0;
	input EPP_AddressStrobe0;
	//SRAM interface signals
	output SRAM_CE;
	output SRAM_OE;
	output SRAM_WE;
	inout [7:0] SRAM_IO;
	output [19:0] SRAM_Addr;
	//
	input clk24;
	input rst;
	output led;

/******************** module regs define ***********************************/
	//regs related to EPP
	reg EPP_Interrupt,EPP_Wait;
	reg EPP_Write,EPP_DataStrobe,EPP_AddressStrobe,EPP_Reset;
	reg [7:0] epp_dataout,epp_datain;
	//regs related to SRAM
	reg SRAM_CE/*,SRAM_OE,SRAM_WE*/;
	reg [19:0] /*SRAM_Addr,*/sram_raddr,sram_waddr;//sram read write address reg
	reg [7:0] sram_dataout;
	//reg sram_readorwrite;//1->read 0->write
	//internal regs
	reg led;
	reg [2:0] epp_state;
	reg [7:0] cmd;//from epp address write

/**********************  module constant define  *******************************/
	//parameters EPP state
	parameter EPP_IDLE=3'b000,EPP_WAIT_ADDRREAD=3'b001,EPP_WAIT_ADDRWRITE=3'b010,
		EPP_WAIT_DATAREAD=3'b011,EPP_WAIT_DATAWRITE=3'b100;


/*********************  module internal logic  *********************************/

//并口输入进来的信号，需要同步。加入锁存器
always @ (posedge clk24)
begin
	if(!rst)
		EPP_Write<=1;
	else
		EPP_Write<=EPP_Write0;
end

always @ (posedge clk24)
begin
	if(!rst)
		EPP_DataStrobe<=1;
	else
		EPP_DataStrobe<=EPP_DataStrobe0;
end

always @ (posedge clk24)
begin
	if(!rst)
		EPP_AddressStrobe<=1;
	else
		EPP_AddressStrobe<=EPP_AddressStrobe0;
end

always @ (posedge clk24)
begin
	if(!rst)
		EPP_Reset<=1;
	else
		EPP_Reset<=EPP_Reset0;
end



//EPP state machine
always @ (posedge clk24)
begin
	if(!rst )
	begin
		epp_state<=EPP_IDLE;
		EPP_Interrupt<=0;
		EPP_Wait<=0;
		epp_dataout<=8'b0;
		epp_datain<=8'b0;
		cmd<=8'b0;
		//SRAM_Addr<=20'b0;
		sram_raddr<=20'b0;
		sram_waddr<=20'd0;
	end
	else
		case(epp_state)
			EPP_IDLE:
			begin
				epp_state<=EPP_IDLE;
				EPP_Wait<=0;
				if(!EPP_AddressStrobe)
				begin
					if(EPP_Write)
					begin//EPP address read
						epp_dataout<=cmd[0]?sram_waddr[7:0]:sram_raddr[7:0];  //8'b0000_1111;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRREAD;
					end
					else
					begin//EPP address write    cmd come from EPP address write
						cmd<=EPP_Data;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRWRITE;
					end
				end
				else if(!EPP_DataStrobe)
				begin
					if(EPP_Write)
					begin//EPP data read
						epp_dataout<=SRAM_IO;//sram_waddr;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAREAD;
					end
					else
					begin//EPP data write
						epp_datain<=EPP_Data;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAWRITE;
					end
				end
			end
			EPP_WAIT_ADDRREAD:
			begin
				if(EPP_AddressStrobe)
				begin
					EPP_Wait<=0;
					//led<=~led;
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_ADDRWRITE:
			begin
				if(EPP_AddressStrobe)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_DATAREAD:
			begin
				if(EPP_DataStrobe)
				begin
					EPP_Wait<=0;
					//led<=~led;
					epp_state<=EPP_IDLE;
					sram_raddr<=sram_raddr+1;
				end
			end
			EPP_WAIT_DATAWRITE:
			begin
				if(EPP_DataStrobe)
				begin
					EPP_Wait<=0;
					//led<=~led;
					epp_state<=EPP_IDLE;
					sram_waddr<=sram_waddr+1;
				end
			end
			default: epp_state<=EPP_IDLE;
		endcase
	end

assign EPP_Data=((epp_state==EPP_WAIT_DATAREAD)||(epp_state==EPP_WAIT_ADDRREAD))?epp_dataout:8'bz;



//cmd resolve


//SRAM 
always @ (posedge clk24)
begin
	if(!rst )
	begin
		led<=1;		
		SRAM_CE<=1;
	end
	else
	begin
		led<=cmd[0];//write to switch led on
		SRAM_CE<=0;//select SRAM all the time
	end
end



assign SRAM_OE=cmd[0];//cmd's LSM 1->write  0->read
assign SRAM_WE=~cmd[0];

assign SRAM_Addr=(cmd[0])?sram_waddr:sram_raddr;
assign SRAM_IO=(cmd[0])?epp_datain:8'bz;

endmodule