t触发器.txt

protel电路板设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch6_1_2a is
    port(
         cp:in std_logic;
         q :out std_logic
         );
end ch6_1_2a;
architecture a of ch6_1_2a is
signal qn: std_logic;
  begin
    process(cp)
      begin
         if cp'event and cp='1'then 
         qn<=not qn;
         end if;
      end process;
      q<=qn;
end a;