add.rpt

protel电路板设计

LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC20 -> - - - * - - - - - - | - * | <-- ~525~1
LC19 -> - - - * - - - - - - | - * | <-- ~525~2
LC18 -> - - - - * - - - - - | - * | <-- ~600~1
LC17 -> - - - - * - - - - - | - * | <-- ~600~2
LC29 -> - - - - * - - - - - | - * | <-- ~600~3

Pin
4    -> * * * - - * * * * * | - * | <-- a0
13   -> * - * - - * * * * * | - * | <-- a1
12   -> * - - * - - - * * * | - * | <-- a2
11   -> * - - - * - - - - - | - * | <-- a3
9    -> * * * - - * * * * * | - * | <-- b0
8    -> * - * - - * * * * * | - * | <-- b1
7    -> * - - * - - - * * * | - * | <-- b2
6    -> * - - - * - - - - - | - * | <-- b3
5    -> * * * - - * - * * - | - * | <-- cin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 c:\documents and settings\add.rpt
add

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
cin      : INPUT;

-- Node name is 'count' 
-- Equation name is 'count', location is LC025, type is output.
 count   = LCELL( _EQ001 $  GND);
  _EQ001 =  a0 &  b0 &  _X001 &  _X002 &  _X003
         #  cin &  _X001 &  _X002 &  _X003 &  _X004
         #  a1 &  b1 &  _X001 &  _X002
         #  a2 &  b2 &  _X002
         #  a3 &  b3;
  _X001  = EXP(!a2 & !b2);
  _X002  = EXP(!a3 & !b3);
  _X003  = EXP(!a1 & !b1);
  _X004  = EXP(!a0 & !b0);

-- Node name is 'sum0' 
-- Equation name is 'sum0', location is LC024, type is output.
 sum0    = LCELL( _EQ002 $  cin);
  _EQ002 =  a0 & !b0
         # !a0 &  b0;

-- Node name is 'sum1' 
-- Equation name is 'sum1', location is LC023, type is output.
 sum1    = LCELL( _EQ003 $  a1);
  _EQ003 =  a0 & !b1 &  cin
         #  b0 & !b1 &  _X005
         # !a0 &  b1 &  _X006
         # !b0 &  b1 & !cin;
  _X005  = EXP(!a0 & !cin);
  _X006  = EXP( b0 &  cin);

-- Node name is 'sum2' 
-- Equation name is 'sum2', location is LC022, type is output.
 sum2    = LCELL( _EQ004 $  _EQ005);
  _EQ004 =  _X007 &  _X008;
  _X007  = EXP(!a2 &  b2);
  _X008  = EXP( a2 & !b2);
  _EQ005 = !_LC019 & !_LC020;

-- Node name is 'sum3' 
-- Equation name is 'sum3', location is LC021, type is output.
 sum3    = LCELL( _EQ006 $  _EQ007);
  _EQ006 =  _X009 &  _X010;
  _X009  = EXP(!a3 &  b3);
  _X010  = EXP( a3 & !b3);
  _EQ007 = !_LC017 & !_LC018 & !_LC029;

-- Node name is '~525~1' 
-- Equation name is '~525~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ008 $  GND);
  _EQ008 =  b0 &  b1 &  cin
         #  a1 &  b0 &  cin
         #  a0 &  b1 &  cin
         #  a0 &  a1 &  cin
         #  a0 &  b0 &  b1;

-- Node name is '~525~2' 
-- Equation name is '~525~2', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ009 $  GND);
  _EQ009 =  a0 &  a1 &  b0
         #  a1 &  b1;

-- Node name is '~600~1' 
-- Equation name is '~600~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ010 $  GND);
  _EQ010 =  b0 &  b1 &  b2 &  cin
         #  a2 &  b0 &  b1 &  cin
         #  a1 &  b0 &  b2 &  cin
         #  a1 &  a2 &  b0 &  cin
         #  a0 &  b1 &  b2 &  cin;

-- Node name is '~600~2' 
-- Equation name is '~600~2', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ011 $  GND);
  _EQ011 =  a0 &  a2 &  b1 &  cin
         #  a0 &  a1 &  b2 &  cin
         #  a0 &  a1 &  a2 &  cin
         #  a0 &  b0 &  b1 &  b2
         #  a0 &  a2 &  b0 &  b1;

-- Node name is '~600~3' 
-- Equation name is '~600~3', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ012 $  GND);
  _EQ012 =  a0 &  a1 &  b0 &  b2
         #  a0 &  a1 &  a2 &  b0
         #  a1 &  b1 &  b2
         #  a1 &  a2 &  b1
         #  a2 &  b2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          c:\documents and settings\add.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,342K