📄 add.rpt
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Project Information c:\documents and settings\add.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/15/2006 10:21:27
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ADD
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
add EPM7032LC44-6 9 5 0 10 10 31 %
User Pins: 9 5 0
Device-Specific Information: c:\documents and settings\add.rpt
add
***** Logic for device 'add' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
R R
c V G G G G G V V
b i a C N N N N N E E
3 n 0 C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
b2 | 7 39 | RESERVED
b1 | 8 38 | RESERVED
b0 | 9 37 | sum3
GND | 10 36 | sum2
a3 | 11 35 | VCC
a2 | 12 EPM7032LC44-6 34 | sum1
a1 | 13 33 | sum0
RESERVED | 14 32 | count
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\documents and settings\add.rpt
add
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 9/16( 56%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 10/16( 62%) 5/16( 31%) 16/16(100%) 14/36( 38%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 14/32 ( 43%)
Total logic cells used: 10/32 ( 31%)
Total shareable expanders used: 10/32 ( 31%)
Total Turbo logic cells used: 10/32 ( 31%)
Total shareable expanders not available (n/a): 6/32 ( 18%)
Average fan-in: 5.50
Total fan-in: 55
Total input pins required: 9
Total output pins required: 5
Total bidirectional pins required: 0
Total logic cells required: 10
Total flipflops required: 0
Total product terms required: 49
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 10
Synthesized logic cells: 5/ 32 ( 15%)
Device-Specific Information: c:\documents and settings\add.rpt
add
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 3 5 a0
13 (9) (A) INPUT 0 0 0 0 0 2 5 a1
12 (8) (A) INPUT 0 0 0 0 0 2 3 a2
11 (7) (A) INPUT 0 0 0 0 0 2 0 a3
9 (6) (A) INPUT 0 0 0 0 0 3 5 b0
8 (5) (A) INPUT 0 0 0 0 0 2 5 b1
7 (4) (A) INPUT 0 0 0 0 0 2 3 b2
6 (3) (A) INPUT 0 0 0 0 0 2 0 b3
5 (2) (A) INPUT 0 0 0 0 0 3 3 cin
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\documents and settings\add.rpt
add
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 25 B OUTPUT t 5 0 1 9 0 0 0 count
33 24 B OUTPUT t 0 0 0 3 0 0 0 sum0
34 23 B OUTPUT t 3 0 1 5 0 0 0 sum1
36 22 B OUTPUT t 2 0 0 2 2 0 0 sum2
37 21 B OUTPUT t 2 0 0 2 3 0 0 sum3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\documents and settings\add.rpt
add
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(38) 20 B SOFT s t 1 0 1 5 0 1 0 ~525~1
(39) 19 B SOFT s t 0 0 0 4 0 1 0 ~525~2
(40) 18 B SOFT s t 1 0 1 7 0 1 0 ~600~1
(41) 17 B SOFT s t 1 0 1 7 0 1 0 ~600~2
(27) 29 B SOFT s t 1 0 1 6 0 1 0 ~600~3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\documents and settings\add.rpt
add
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------- LC25 count
| +----------------- LC24 sum0
| | +--------------- LC23 sum1
| | | +------------- LC22 sum2
| | | | +----------- LC21 sum3
| | | | | +--------- LC20 ~525~1
| | | | | | +------- LC19 ~525~2
| | | | | | | +----- LC18 ~600~1
| | | | | | | | +--- LC17 ~600~2
| | | | | | | | | +- LC29 ~600~3
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'B'
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