test2.vhd

VHDL写的LMS算法程序。利用本地正弦信号

-- VHDL Test Bench Created from source file lms.vhd -- 20:25:36 07/03/2005
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE     IEEE.STD_LOGIC_1164.ALL;
USE     IEEE.NUMERIC_STD.ALL;
USE     IEEE.STD_LOGIC_ARITH.ALL;
USE     IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY testbench IS
END testbench;



ARCHITECTURE behavior OF testbench IS 



  COMPONENT cosfunc_test
    PORT (
            THETA   : IN  std_logic_VECTOR(4 downto 0);
            CLK     : IN  std_logic;
            ACLR    : IN  std_logic;
            COSINE  : OUT std_logic_VECTOR(7 downto 0)
          );
    END COMPONENT;



	SIGNAL CLK     :  std_logic;
	SIGNAL start   :  std_logic;
     SIGNAL ACLR    :  std_logic;

     SIGNAL THETA   :  std_logic_vector(4 downto 0);
	SIGNAL wave    :  std_logic_vector(7 downto 0);





BEGIN


     U2: cosfunc_test
             PORT MAP(
                       THETA   => THETA,
                       CLK     => CLK,
                       ACLR    => ACLR,
                       COSINE  => wave
				  );
 


------------------------------------------------------------------------------------------

Initial : PROCESS
   
	           BEGIN
	 
	              start <='0';
	              ACLR  <='1';  
				           WAIT FOR 15.0 ns;
			    start <='1';
			    ACLR  <='0';
				           WAIT;
   
	       END PROCESS;

------------------------------------------------------------------------------------------

sTHETA:PROCESS
		 
		   BEGIN	  	     		
		 
			   WAIT UNTIL ( clk'EVENT AND clk='1' );
							  
							  IF(start = '1') THEN			   -- "start" signal.

							     THETA <= THETA + 1;	                                       
							  
							  ELSE

								THETA  <= "00000";
							  
							  END IF;               

		   END PROCESS;	


------------------------------------------------------------------------------------------

ClkGenerate: PROCESS
	         
			   BEGIN
		
		              WAIT FOR 10.0ns;                -- Clock: 100MHz 
		                  
					   IF CLK  = '1' then			               
						 CLK <= '0';		        
			             ELSE
			                CLK <= '1';
		                  END IF;
	      
		    END PROCESS;




END behavior;