lms.syr

VHDL写的LMS算法程序。利用本地正弦信号

Release 6.2i - xst G.31a
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: lms.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : lms.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : lms
Output Format                      : NGC
Target Device                      : xc2v80-4-cs144

---- Source Options
Top Module Name                    : lms
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lms.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS4\FPGA_LMS3/costest.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS4\FPGA_LMS3/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS4/FPGA_LMS3/PCK_S2V.vhd in Library work.
Architecture pck_s2v of Entity pck_s2v is up to date.
Compiling vhdl file F:/FPGA_LMS4/FPGA_LMS3/LMS.vhd in Library work.
Architecture behav of Entity lms is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lms> (Architecture <behav>).
WARNING:Xst:766 - F:/FPGA_LMS4/FPGA_LMS3/LMS.vhd line 113: Generating a Black Box for component <cosfunc>.
WARNING:Xst:766 - F:/FPGA_LMS4/FPGA_LMS3/LMS.vhd line 128: Generating a Black Box for component <costest>.
INFO:Xst:1304 - Contents of register <ND> in unit <lms> never changes during circuit operation. The register is replaced by logic.
Entity <lms> analyzed. Unit <lms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lms>.
    Related source file is F:/FPGA_LMS4/FPGA_LMS3/LMS.vhd.
WARNING:Xst:646 - Signal <TestRFD> is assigned but never used.
WARNING:Xst:646 - Signal <RFD> is assigned but never used.
    Found 8-bit register for signal <waveOut>.
    Found 8-bit register for signal <eOut>.
    Found 8x8-bit multiplier for signal <$n0003> created at line 190.
    Found 8x8-bit multiplier for signal <$n0005> created at line 216.
    Found 10x8-bit multiplier for signal <$n0007> created at line 245.
    Found 10x8-bit multiplier for signal <$n0009> created at line 268.
    Found 10-bit adder for signal <$n0011> created at line 292.
    Found 8-bit subtractor for signal <$n0032> created at line 296.
    Found 1-bit register for signal <ACLR>.
    Found 8-bit register for signal <err>.
    Found 6-bit up counter for signal <INT_sTHETA>.
    Found 6-bit up counter for signal <INT_THETA>.
    Found 10-bit register for signal <Qcos>.
    Found 10-bit register for signal <Qsin>.
    Found 6-bit register for signal <sTHETA>.
    Found 6-bit register for signal <THETA>.
    Found 10-bit up accumulator for signal <Wcos>.
    Found 10-bit up accumulator for signal <Wsin>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 Accumulator(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   4 Multiplier(s).
Unit <lms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Found registered multiplier on the signal <_n0007> with 1 register level(s).
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                      : 4
 10x8-bit multiplier               : 1
 8x8-bit multiplier                : 2
 10x8-bit registered multiplier    : 1
# Adders/Subtractors               : 2
 8-bit subtractor                  : 1
 10-bit adder                      : 1
# Counters                         : 2
 6-bit up counter                  : 2
# Accumulators                     : 2
 10-bit up accumulator             : 2
# Registers                        : 7
 8-bit register                    : 3
 6-bit register                    : 2
 1-bit register                    : 1
 10-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "costest.ngo" is up to date.
Launcher: "cosfunc.ngo" is up to date.
Loading core <costest> for timing and area information for instance <U2>.
Loading core <cosfunc> for timing and area information for instance <U1>.
WARNING:Xst:1291 - FF/Latch <Qsin_9> is unconnected in block <lms>.
WARNING:Xst:1291 - FF/Latch <Qsin_8> is unconnected in block <lms>.

Optimizing unit <lms> ...
Loading device for application Xst from file '2v80.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 13.
WARNING:Xst:382 - Register BU30 is equivalent to BU15
WARNING:Xst:382 - Register BU32 is equivalent to BU17
WARNING:Xst:382 - Register BU34 is equivalent to BU19
WARNING:Xst:382 - Register BU36 is equivalent to BU21
WARNING:Xst:382 - Register BU38 is equivalent to BU23
WARNING:Xst:382 - Register BU40 is equivalent to BU25
FlipFlop err_7 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lms.ngr
Top Level Output File Name         : lms
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Macro Statistics :
# Registers                        : 65
#      1-bit register              : 61
#      6-bit register              : 2
#      8-bit register              : 2
# Adders/Subtractors               : 6
#      10-bit adder                : 3
#      6-bit adder                 : 2
#      8-bit subtractor            : 1
# Multipliers                      : 4
#      10x8-bit multiplier         : 1
#      10x8-bit registered multiplier: 1
#      8x8-bit multiplier          : 2

Cell Usage :
# BELS                             : 146
#      GND                         : 3
#      LUT1                        : 13
#      LUT2                        : 1
#      LUT2_L                      : 34
#      LUT3                        : 3
#      LUT4                        : 4
#      MUXCY                       : 42
#      VCC                         : 3
#      XORCY                       : 43
# FlipFlops/Latches                : 126
#      FDCE                        : 30
#      FDE                         : 46
#      FDR                         : 45
#      FDS                         : 5
# RAMS                             : 2
#      RAMB16_S9                   : 1
#      RAMB16_S9_S9                : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 1
#      OBUF                        : 24
# MULTs                            : 4
#      MULT18X18                   : 3
#      MULT18X18S                  : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v80cs144-4 

 Number of Slices:                      73  out of    512    14%  
 Number of Slice Flip Flops:           126  out of   1024    12%  
 Number of 4 input LUTs:                55  out of   1024     5%  
 Number of bonded IOBs:                 25  out of     92    27%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of MULT18X18s:                   4  out of      8    50%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 129   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.147ns (Maximum Frequency: 122.748MHz)
   Minimum input arrival time before clock: 3.648ns
   Maximum output required time after clock: 5.630ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               8.147ns (Levels of Logic = 5)
  Source:            U1/BU64 (FF)
  Destination:       Wsin_9 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: U1/BU64 to Wsin_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            22   0.568   1.052  BU64 (SINE<7>)
     end scope: 'U1'
     MULT18X18:B8->P15     2   3.444   0.701  Mmult__n0005_inst_mult_1 (_n0005<15>)
     LUT2_L:I0->LO         1   0.439   0.000  Wsin_Madd__n0000_inst_lut2_321 (Wsin_Madd__n0000_inst_lut2_32)
     MUXCY:S->O            0   0.298   0.000  Wsin_Madd__n0000_inst_cy_31 (Wsin_Madd__n0000_inst_cy_31)
     XORCY:CI->O           1   1.274   0.000  Wsin_Madd__n0000_inst_sum_33 (Wsin__n0000<9>)
     FDR:D                     0.370          Wsin_9
    ----------------------------------------
    Total                      8.147ns (6.393ns logic, 1.754ns route)
                                       (78.5% logic, 21.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              3.648ns (Levels of Logic = 2)
  Source:            start (PAD)
  Destination:       Wcos_7 (FF)
  Destination Clock: CLK rising

  Data Path: start to Wcos_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            16   0.825   1.000  start_IBUF (start_IBUF)
     LUT3:I1->O           38   0.439   1.103  Qsin_9_N2401 (Qsin_9_N240)
     FDS:S                     0.280          Qsin_6
    ----------------------------------------
    Total                      3.648ns (1.544ns logic, 2.104ns route)
                                       (42.3% logic, 57.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              5.630ns (Levels of Logic = 2)
  Source:            U2/BU42 (FF)
  Destination:       waveIN<7> (PAD)
  Source Clock:      CLK rising

  Data Path: U2/BU42 to waveIN<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.568   0.701  BU42 (SINE<7>)
     end scope: 'U2'
     OBUF:I->O                 4.361          waveIN_7_OBUF (waveIN<7>)
    ----------------------------------------
    Total                      5.630ns (4.929ns logic, 0.701ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 13.55 / 14.89 s | Elapsed : 14.00 / 15.00 s
 
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Total memory usage is 71020 kilobytes