lms.gfl

来自「VHDL写的LMS算法程序。利用本地正弦信号」· GFL 代码 · 共 1,072 行 · 第 1/2 页

GFL
1,072 行
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12
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# View RTL Schematic
lms.ngr
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# VHDL : View VHDL Instantiation Template
__projnav/tb.rsp
lms.vhi
__projnav/vhd2vhi.err
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
test_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_fortest_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
12

lms.gfl - 源码说明

本页面展示了「VHDL写的LMS算法程序。利用本地正弦信号」中的 lms.gfl 源码文件，采用 GFL 编程语言编写，共 1,072 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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