ram_sel_wdrd.v

来自「此代码可用modelsim进行仿真」· Verilog 代码 · 共 19 行

/*****************************************/
/**        8bit RISC MCU desing         **/
/**         ram_sel_wdrd module         **/
/**            BY yuzhijie              **/
/**            2006.10.30               **/
/*****************************************/
`timescale 1ns/100ps
module ram_sel_wdrd(sel_wd,fsr_out,dir_addr,in_wdrd);
    input sel_wd;
    input [7:0]dir_addr;
    input [7:0]fsr_out;
    output [7:0]in_wdrd;
    //sel_wd :sel direct or indirect;1:indirect;0:direct
    //fsr_out :indirect input
    //dir_addr :direct input
    //in_wdrd :address of ram
    assign in_wdrd=sel_wd?fsr_out:dir_addr;
endmodule