clock.v

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/*****************************************/
/**        8bit RISC MCU desing         **/
/**           clock module              **/
/**            BY yuzhijie              **/
/**            2006.10.22               **/
/*****************************************/
`timescale 1ns/100ps
module clock(clk,reset,clk1,clk2,clk3,clk4);
    input clk,reset;
    output clk1,clk2,clk3,clk4;
    wire clk,reset;          
    reg clk1,clk2,clk3,clk4;
    reg [3:0]state;
    parameter s1=4'b0001,
              s2=4'b0010,
              s3=4'b0100,
              s4=4'b1000;
    always@(posedge clk)
    if(reset)
    begin
        clk1<=1'b0;
        clk2<=1'b0;
        clk3<=1'b0;
        clk4<=1'b1;
        state<=s1;
    end
    else
    begin
        case(state)
            s1:
            begin
                clk1<=~clk1;
                clk4<=~clk4;
                state<=s2;
            end
            s2:
            begin
                clk1<=~clk1;
                clk2<=~clk2;
                state<=s3;
            end
            s3:
            begin
                clk2<=~clk2;
                clk3<=~clk3;
                state<=s4;
            end
            s4:
            begin
                clk3<=~clk3;
                clk4<=~clk4;
                state<=s1;
            end
            default:state<=s1;
    endcase
end
endmodule