pc.v

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/*****************************************/
/**        8bit RISC MCU desing         **/
/**            pc module                **/
/**            BY yuzhijie              **/
/**            2006.11.19               **/
/*****************************************/
`timescale 1ns/100ps
module pc(clk4,reset,load_pc,load_pc_goto,load_pc_call,
          stack1,load_pc_retlw,literal,pc_addr);//status
    input clk4,reset,load_pc,load_pc_goto,load_pc_call,load_pc_retlw;
   // input [1:0]status;
    input [10:0]stack1;
    input [8:0]literal;
    output [10:0]pc_addr;
    reg [10:0]pc_addr;
    reg stateh;
    parameter t1=1'b0;
    always@(posedge clk4)
    begin
        if(reset==1)
        begin
           pc_addr<=11'h7ff;
        end
        else if(load_pc==0)
            begin
                pc_addr<=pc_addr+1;
            end
        else if(load_pc==1&&load_pc_call==1)//CALL
            begin
                 pc_addr[10:0]<={2'b00,1'b0,literal[7:0]};
               /*case(stateh)
              
                   t1:
                   begin
                   pc_addr[10:0]<={2'b00,1'b0,literal[7:0]};
                   stateh<=1'b1;
                   end
                                     
                   default :
                   begin 
                   pc_addr<=pc_addr;
                   stateh<=1'b0;
                   end
               endcase*/
            end
            else if(load_pc==1&&load_pc_goto==1)//goto
            begin
                pc_addr[10:0]<={2'b00,literal[8:0]};
               /*case(stateh)
              
                   t1:
                   begin
                   pc_addr[10:0]<={2'b00,literal[8:0]};
                   stateh<=1'b1;
                   end
                                     
                   default :
                   begin 
                   pc_addr<=pc_addr;
                   stateh<=1'b0;
                   end
               endcase*/
            end
            else if(load_pc==1&&load_pc_retlw==1)//RETLW
            begin
                pc_addr<=stack1;
              /* case(stateh)
              
                   t1:
                   begin
                   pc_addr<=stack1;
                   stateh<=1'b1;
                   end
                                     
                   default :
                   begin 
                   pc_addr<=pc_addr;
                   stateh<=1'b0;
                   end
               endcase*/
            end
         end
endmodule