test1_cpu.v.bak

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/*****************************************/
/**        8bit RISC MCU desing         **/
/**          test1_cpu module           **/
/**            BY yuzhijie              **/
/**            2006.11.2                **/
/*****************************************/
`include"alu.v"
`include"clock.v"
`include"encode.v"
`include"ir.v"
`include"pc.v"
`include"ram_sel_wdrd.v"
`include"sel_tmp2.v"
`include"stack.v"
`include"w.v"
`timescale 1ns/100ps
module test1_cpu;
    reg clk,reset;
    reg [11:0]instruction;
    reg [7:0]ram_out,fsr_out;
    //clock
    wire clk1,clk2,clk3,clk4;
    //stack
    wire [10:0]pc_addr;
    wire [10:0]stack1;
    //pc
    wire load_pc,load_pc_call,load_pc_goto,load_pc_retlw;
    //ir
    wire ir_jump;
    //encode
    wire sel_imm,sel_wd,w_reg,r_reg,w_ena;
    wire [4:0]choice;
    wire [11:0]encode;
    //ram_sel_wdrd
    wire [7:0]in_wdrd;
    //w
    wire [7:0]alu_out;
    //sel_tmp2
    wire [7:0]tmp2;
    //alu
    wire [7:0]tmp1;
    wire alu_z;
    clock
    clock1(.clk(clk),.reset(reset),.clk1(clk1),.clk2(clk2),
           .clk3(clk3),.clk4(clk4));
    stack
    stack2(.clk4(clk4),.pc_addr(pc_addr),.stack_call(load_pc_call),
           .stack_retlw(load_pc_retlw),.stack1(stack1));
    pc
    pc1(.clk4(clk4),.reset(reset),.load_pc(load_pc),.load_pc_call(load_pc_call),
        .load_pc_goto(load_pc_goto),.load_pc_retlw(load_pc_retlw),.stack1(stack1),
        .literal(encode[8:0]),.pc_addr(pc_addr));
    ir
    ir1(.clk1(clk1),.instruction(instruction),.ir_jump(ir_jump),.ir_out(encode),
        .reset(reset));
    encode
    encode1(.clk2(clk2),.reset(reset),.encode(encode),.choice(choice),
            .sel_imm(sel_imm),.sel_wd(sel_wd),.load_pc(load_pc),.w_reg(w_reg),
            .r_reg(r_reg),.w_ena(w_ena),.ir_jump(ir_jump),.load_pc_call(load_pc_call),
            .load_pc_goto(load_pc_goto),.load_pc_retlw(load_pc_retlw),.alu_z(alu_z),
            .alu_bitz(alu_bitz));
    sel_tmp2
    sel_tmp21(.ram_out(ram_out),.literalk(encode[7:0]),.tmp2(tmp2),.sel_imm(sel_imm));
    w
    w1(.clk1(clk1),.reset(reset),.w_ena(w_ena),.w_out(tmp1),
       .alu_out(alu_out));
    alu
    alu1(.clk4(clk4),.tmp1(tmp1),.tmp2(tmp2),.choice(choice),.alu_out(alu_out)
         ,.alu_z(alu_z),.alu_bitz(alu_bitz));
    ram_sel_wdrd
    ram_sel_wdrd1(.dir_addr({3'b000,encode[4:0]}),.fsr_out(fsr_out),.sel_wd(sel_wd),
                  .in_wdrd(in_wdrd));
    initial
    begin
        clk=1;
        reset=1;
        #199 ram_out=8'b0100110;                                                                                 
             //fsr_out=8'b00100101;
             reset=0;
           instruction=12'b0000_0000_0000;
           #800 instruction=12'b0000_0000_0000;
           #800 instruction=12'b0000_0000_0000;
           #800 instruction=12'b0000_0000_0000;
           #800 instruction=12'b0000_0000_0000;
           #800 instruction=12'b0100_1010_0000;//BCF
           #800 instruction=12'b0010_0010_0000;//MOVF
           #800 instruction=12'b0101_1010_0000;//BSF
           #800 instruction=12'b0010_0010_0000;//MOVF 
           #800 instruction=12'b0000_0000_0000;
           
          
        #800 reset=1;
        #3000 $stop;
    end
    always #50 clk=~clk;
endmodule




 /* instruction=12'b1011_1100_1001;//GOTO
           #400instruction=12'b1011_1100_1001;
           instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0110;
        #400 instruction=12'b1000_1100_1100;//RETLW
        #400 instruction=12'b1000_1100_1100;
        #400 instruction=12'b1001_1000_0001;//CALL
        #400 instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0000;
           #400 instruction=12'b0000_0000_0000;
        #400 instruction=12'b1001_1000_0001;
        #400 instruction=12'b1000_1100_1100;
        #400 instruction=12'b1000_1100_1100;
        instruction=12'b0110_0110_1000;//BTFSC
        #400 instruction=12'b1100_1010_1010;//MOVLW
        #400 instruction=12'b0111_0110_0000;//BTFSS
        #400 instruction=12'b1100_1010_1010;//MOVLW
        instruction=12'b1100_1010_1010;//MOVLW
        #400 instruction=12'b0010_1100_1100;//DECFSZ
        #400 instruction=12'b0010_1100_1100;
        #400 instruction=12'b0010_1100_1100;
        #400 instruction=12'b0001_0000_0000;//ADDWF
        #400 instruction=12'b0001_0100_1111;//ANDWF
        #400 instruction=12'b0001_0011_1111;//IORWF
        #400 instruction=12'b0011_0100_0000;//RLF
        #400 instruction=12'b0011_0000_0000;//RRF
        #400 instruction=12'b0000_1000_0000;//SUBWF
        #400 instruction=12'b0011_1000_0000;//SWAPF
        #400 instruction=12'b0001_1000_0000;//XORWF
        #400 instruction=12'b1110_0101_0101;//ANDLW
        #400 instruction=12'b1101_1010_1010;//IORLW
        #400 instruction=12'b1111_1111_0000;//XORLW
        #400 instruction=12'b0010_0111_0000;//COMF
        #400 instruction=12'b0010_0010_1001;//MOVF
        #400 instruction=12'b0100_1011_1111;//BCF
        #400 instruction=12'b0101_1010_0000;//BSF
        */