w.v.bak

此代码可用modelsim进行仿真

/*****************************************/
/**        8bit RISC MCU desing         **/
/**             w module                **/
/**            BY yuzhijie              **/
/**            2006.11.3              **/
/*****************************************/
`timescale 1ns/100ps
module w(alu_out,w_ena,w_out,clk1,reset);
    input clk1,reset,w_ena;
    input[7:0]alu_out;
    output [7:0]w_out;
    reg [7:0]w_out;
    always@(posedge clk1)
    begin
        if(reset)
        begin
            w_out<=8'bxxxx_xxxx;
        end
        if(w_ena)
        begin
            w_out<=alu_out;
        end
        else
        begin
            w_out<=8'bzzzz_zzzz;
    end
endmodule