alu.v.bak

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/*****************************************/
/**        8bit RISC MCU desing         **/
/**            alu module               **/
/**            BY yuzhijie              **/
/**            2006.10.30               **/
/*****************************************/
`timescale 1ns/100ps
module alu(clk4,tmp1,tmp2,choice,alu_out,alu_z,alu_bitz);
           
           // clk : clock
           // tmp1 : input of w_reg
           // tmp2 : input of literal or ram_reg 
           // choice : choose alu
           // bbb : choose zhe bit of f
           // cin : for 9bit + or - 
           // alu_out :output of alu
           // alu_c : 8 bit carry or borrow
           // alu_dc : 4bit carry or borrow
           // alu_z : alu if output is 0,alu_z=1
           // alu_bitz :operate bit is 0, alu_z_b=1
  input clk4;//cin;
  input [7:0]tmp1,tmp2;
  //input [2:0]bbb;
  input [4:0]choice;
  //output alu_c,alu_dc,alu_z,alu_z_b;
  output[7:0]alu_out;
  output alu_z,alu_bitz;
  reg [7:0]alu_out;
  //reg alu_bitz;
  //reg alu_c,alu_dc,alu_bitz;
  parameter  ADDWF=5'b00000,//w reg+f reg;
             MOVLW=5'b00001,//move literal to w reg
             ANDWF=5'b00010,//w and f
             CLRF=5'b00011,//clear f reg
             CLRW=5'b00100,//clear w reg
             IORWF=5'b00101,//w or f
             MOVF=5'b00110,//move f to destination by d=0 or 1
             MOVWF=5'b00111,//move f to w
             NOP=5'b01000,//nop
             RLF=5'b01001,//move left
             RRF=5'b01010,//move right
             SUBWF=5'b01011,//w-f
             SWAPF=5'b01100,//swap f
             XORWF=5'b01101,//w or f
             ANDLW=5'b01110,//literalk and w
             IORLW=5'b01111,//literalk or w
             XORLW=5'b10000,//literalk xor w
             COMF=5'b10001,//the contents of f reg are complemented
             BCF=5'b10010,//clear bit to 0
             BSF=5'b10011,//put bit to 1
             DECF=5'b10100,//sub 1
             INCF=5'b10101,//add 1
             DECFSZ=5'b10110,//sub 1 when tmp1 is not 0
             INCFSZ=5'b10111,//add 1 when tmp1 is not 2'hff
             BTFSC=5'b11000,//bit in f reg is 0 then skip
             BTFSS=5'b11001,//bit in f reg is 1 then skip
             CALL=5'b11010,//push
             RETLW=5'b11011,//pull
             GOTO=5'b11100,//
             TRIS=5'b11101;//control I/O
assign alu_z=!(tmp1);
assign alu_bitz=tmp2[tmp2[7:5]];
  always @(posedge clk4)
  begin
      casex(choice)
          ADDWF  : alu_out<=tmp1+tmp2;
          MOVLW  : alu_out<=tmp2;
          ANDWF  : alu_out<=(tmp1)&(tmp2);
          CLRF   : alu_out<=8'b0000_0000;
          CLRW   : alu_out<=8'b0000_0000;
          IORWF  : alu_out<=(tmp1)|(tmp2);
          MOVF   : alu_out<=tmp2;
          MOVWF  : alu_out<=tmp2;
          NOP    : alu_out<=tmp2;
          RLF    : alu_out<=tmp2<<1;
          RRF    : alu_out<=tmp2>>1;
          SUBWF  : alu_out<=(tmp1)-(tmp2);
          SWAPF  : 
               begin 
                   alu_out[7:4]<=tmp2[3:0];
                   alu_out[3:0]<=tmp2[7:4];
               end
          XORWF  : alu_out<=(tmp1)^(tmp2);
          ANDLW  : alu_out<=(tmp1)&(tmp2);
          IORLW  : alu_out<=(tmp1)|(tmp2);
          XORLW  : alu_out<=tmp1^tmp2;
          COMF   : alu_out<=tmp2^8'b1111_1111;
          BCF    : 
               begin
                   if(tmp2[7:5]==0)
                   begin
                       alu_out[0]<=0;
                       alu_out[7:1]<=tmp2[7:1];
                   end
                   else if(tmp2[7:5]==1)
                   begin
                       alu_out[1]<=0;
                       alu_out[7:2]<=tmp2[7:2];
                       alu_out[0]<=tmp2[0];
                   end
                   else if(tmp2[7:5]==2)
                   begin
                       alu_out[2]<=0;
                       alu_out[7:3]<=tmp2[7:3];
                       alu_out[1:0]<=tmp2[1:0];
                   end
                   else if(tmp2[7:5]==3)
                   begin
                       alu_out[3]<=0;
                       alu_out[7:4]<=tmp2[7:4];
                       alu_out[2:0]<=tmp2[2:0];
                   end
                   else if(tmp2[7:5]==4)
                   begin
                       alu_out[4]<=0;
                       alu_out[7:5]<=tmp2[7:5];
                       alu_out[3:0]<=tmp2[3:0];
                   end
                   else if(tmp2[7:5]==5)
                   begin
                       alu_out[5]<=0;
                       alu_out[7:6]<=tmp2[7:6];
                       alu_out[4:0]<=tmp2[4:0];
                   end
                   else if(tmp2[7:5]==6)
                   begin
                       alu_out[6]<=0;
                       alu_out[7]<=tmp2[7];
                       alu_out[5:0]<=tmp2[5:0];
                   end
                   else if(tmp2[7:5]==7)
                   begin
                       alu_out[7]<=0;
                       alu_out[6:0]<=tmp2[6:0];
                   end
               end
          BSF    : 
               begin
                   if(tmp2[7:5]==0)
                   begin
                       alu_out[0]<=1;
                       alu_out[7:1]<=tmp2[7:1];
                   end
                   else if(tmp2[7:5]==1)
                   begin
                       alu_out[1]<=1;
                       alu_out[7:2]<=tmp2[7:2];
                       alu_out[0]<=tmp2[0];
                   end
                   else if(tmp2[7:5]==2)
                   begin
                       alu_out[2]<=1;
                       alu_out[7:3]<=tmp2[7:3];
                       alu_out[1:0]<=tmp2[1:0];
                   end
                   else if(tmp2[7:5]==3)
                   begin
                       alu_out[3]<=1;
                       alu_out[7:4]<=tmp2[7:4];
                       alu_out[2:0]<=tmp2[2:0];
                   end
                   else if(tmp2[7:5]==4)
                   begin
                       alu_out[4]<=1;
                       alu_out[7:5]<=tmp2[7:5];
                       alu_out[3:0]<=tmp2[3:0];
                   end
                   else if(tmp2[7:5]==5)
                   begin
                       alu_out[5]<=1;
                       alu_out[7:6]<=tmp2[7:6];
                       alu_out[4:0]<=tmp2[4:0];
                   end
                   else if(tmp2[7:5]==6)
                   begin
                       alu_out[6]<=1;
                       alu_out[7]<=tmp2[7];
                       alu_out[5:0]<=tmp2[5:0];
                   end
                   else if(tmp2[7:5]==7)
                   begin
                       alu_out[7]<=1;
                       alu_out[6:0]<=tmp2[6:0];
                   end
               end
          DECF   : alu_out<=tmp1-1;
          INCF   : alu_out<=tmp1+1;
          DECFSZ : alu_out<=tmp1-1;
          INCFSZ : alu_out<=tmp1+1;
          BTFSC  : alu_out<=tmp2;
          BTFSS  : alu_out<=tmp2;
          CALL   : alu_out<=tmp2;
          RETLW  : alu_out<=tmp2;
          GOTO   : alu_out<=tmp2;
          TRIS   : alu_out<=tmp1;
          default:alu_out<=8'bxxxx_xxxx;
  endcase
  end
  endmodule