ir.v.bak

此代码可用modelsim进行仿真

/*****************************************/
/**        8bit RISC MCU desing         **/
/**            ir module                **/
/**            BY yuzhijie              **/
/**            2006.10.22               **/
/*****************************************/
`timescale 1ns/100ps
module ir(instruction,reset,clk1,ir_jump,ir_out);
    input clk1,reset,ir_jump;       //jump ena
    input [11:0]instruction;  
    output [11:0]ir_out;      //ir's output
    reg [11:0]ir_out;    
    always@(posedge clk1 or reset)
    begin
        if(reset)
        begin
            ir_out<=12'b0000_0000_0000;
        end
        else if(ir_jump==1)
        begin
            ir_out<=12'b0000_0000_0000;    //nop
        end
        else
        begin
            ir_out<=instruction;
        end
    end
endmodule