_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ram_sel_wdrd is
    port(
        sel_wd          : in     vl_logic;
        fsr_out         : in     vl_logic_vector(7 downto 0);
        dir_addr        : in     vl_logic_vector(7 downto 0);
        in_wdrd         : out    vl_logic_vector(7 downto 0)
    );
end ram_sel_wdrd;