_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity pc is
    generic(
        t1              : integer := 0
    );
    port(
        clk4            : in     vl_logic;
        reset           : in     vl_logic;
        load_pc         : in     vl_logic;
        load_pc_goto    : in     vl_logic;
        load_pc_call    : in     vl_logic;
        stack1          : in     vl_logic_vector(10 downto 0);
        load_pc_retlw   : in     vl_logic;
        \literal\       : in     vl_logic_vector(8 downto 0);
        pc_addr         : out    vl_logic_vector(10 downto 0)
    );
end pc;