_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity clock is
    generic(
        s1              : integer := 1;
        s2              : integer := 2;
        s3              : integer := 4;
        s4              : integer := 8
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        clk1            : out    vl_logic;
        clk2            : out    vl_logic;
        clk3            : out    vl_logic;
        clk4            : out    vl_logic
    );
end clock;