_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity encode is
    port(
        clk2            : in     vl_logic;
        reset           : in     vl_logic;
        encode          : in     vl_logic_vector(11 downto 0);
        alu_z           : in     vl_logic;
        alu_bitz        : in     vl_logic;
        choice          : out    vl_logic_vector(4 downto 0);
        sel_imm         : out    vl_logic;
        sel_wd          : out    vl_logic;
        load_pc         : out    vl_logic;
        load_pc_call    : out    vl_logic;
        load_pc_goto    : out    vl_logic;
        load_pc_retlw   : out    vl_logic;
        w_reg           : out    vl_logic;
        r_reg           : out    vl_logic;
        w_ena           : out    vl_logic;
        ir_jump         : out    vl_logic
    );
end encode;