latch1.fit.summary

来自「FPGA光电编码器输入模块」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Wed Jun 14 11:02:01 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : LATCH1
Top-level Entity Name : LATCH1
Family : Cyclone II
Device : EP2C5Q208C8
Timing Models : Preliminary
Total logic elements : 16 / 4,608 ( < 1 % )
Total registers : 16
Total pins : 34 / 142 ( 24 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )