latch1.map.qmsg

FPGA光电编码器输入模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 14 11:01:40 2006 " "Info: Processing started: Wed Jun 14 11:01:40 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LATCH1 -c LATCH1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LATCH1 -c LATCH1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LATCH1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LATCH1.v" { { "Info" "ISGN_ENTITY_NAME" "1 LATCH1 " "Info: Found entity 1: LATCH1" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LATCH1 " "Info: Elaborating entity \"LATCH1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "PUSLE_COUNT LATCH1.v(7) " "Info (10035): Verilog HDL or VHDL information at LATCH1.v(7): object \"PUSLE_COUNT\" declared but not used" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 7 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "REG_TEMP LATCH1.v(18) " "Warning (10235): Verilog HDL Always Construct warning at LATCH1.v(18): variable \"REG_TEMP\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 18 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 14 11:01:42 2006 " "Info: Processing ended: Wed Jun 14 11:01:42 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}