📄 latch1.fit.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 14 11:01:47 2006 " "Info: Processing started: Wed Jun 14 11:01:47 2006" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LATCH1 -c LATCH1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LATCH1 -c LATCH1" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "LATCH1 EP2C5Q208C8 " "Info: Selected device EP2C5Q208C8 for design \"LATCH1\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208C8 " "Info: Device EP2C8Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "34 34 " "Info: No exact pin location assignment(s) for 34 pins of 34 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[0\] " "Info: Pin PC_OUT\[0\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[1\] " "Info: Pin PC_OUT\[1\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[2\] " "Info: Pin PC_OUT\[2\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[3\] " "Info: Pin PC_OUT\[3\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[4\] " "Info: Pin PC_OUT\[4\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[5\] " "Info: Pin PC_OUT\[5\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[5] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[6\] " "Info: Pin PC_OUT\[6\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[7\] " "Info: Pin PC_OUT\[7\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[8\] " "Info: Pin PC_OUT\[8\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[9\] " "Info: Pin PC_OUT\[9\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[10\] " "Info: Pin PC_OUT\[10\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[11\] " "Info: Pin PC_OUT\[11\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[12\] " "Info: Pin PC_OUT\[12\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[13\] " "Info: Pin PC_OUT\[13\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[14\] " "Info: Pin PC_OUT\[14\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[15\] " "Info: Pin PC_OUT\[15\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CE " "Info: Pin CE not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { CE } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CLR } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { CLR } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[0\] " "Info: Pin PULSE_COUNT\[0\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[1\] " "Info: Pin PULSE_COUNT\[1\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[2\] " "Info: Pin PULSE_COUNT\[2\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[3\] " "Info: Pin PULSE_COUNT\[3\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[4\] " "Info: Pin PULSE_COUNT\[4\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[5\] " "Info: Pin PULSE_COUNT\[5\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[5] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[6\] " "Info: Pin PULSE_COUNT\[6\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[7\] " "Info: Pin PULSE_COUNT\[7\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[8\] " "Info: Pin PULSE_COUNT\[8\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[9\] " "Info: Pin PULSE_COUNT\[9\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[10\] " "Info: Pin PULSE_COUNT\[10\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[11\] " "Info: Pin PULSE_COUNT\[11\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[12\] " "Info: Pin PULSE_COUNT\[12\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[13\] " "Info: Pin PULSE_COUNT\[13\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[14\] " "Info: Pin PULSE_COUNT\[14\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[15\] " "Info: Pin PULSE_COUNT\[15\] not assigned to an exact location on the device" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PULSE_COUNT[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CE (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CE (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[15\] " "Info: Destination node PC_OUT\[15\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[15] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[14\] " "Info: Destination node PC_OUT\[14\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[14] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[13\] " "Info: Destination node PC_OUT\[13\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[13] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[12\] " "Info: Destination node PC_OUT\[12\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[12] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[11\] " "Info: Destination node PC_OUT\[11\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[11] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[10\] " "Info: Destination node PC_OUT\[10\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[10] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[9\] " "Info: Destination node PC_OUT\[9\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[9] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[8\] " "Info: Destination node PC_OUT\[8\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[8] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[7\] " "Info: Destination node PC_OUT\[7\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[7] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[6\] " "Info: Destination node PC_OUT\[6\]" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PC_OUT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { PC_OUT[6] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" { Floorplan "D:/altera/fpga+dsp/LATCH1/LATCH1.fld" "" "" { CE } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
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