latch1.tan.qmsg

FPGA光电编码器输入模块

{ "Info" "ITDB_FULL_TCO_RESULT" "CE PC_OUT\[7\] REG_TEMP\[7\] 7.618 ns register " "Info: tco from clock \"CE\" to destination pin \"PC_OUT\[7\]\" through register \"REG_TEMP\[7\]\" is 7.618 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CE source 2.790 ns + Longest register " "Info: + Longest clock path from clock \"CE\" to source register is 2.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CE~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "0.143 ns" { CE CE~clkctrl } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(0.666 ns) 2.790 ns REG_TEMP\[7\] 3 REG LCFF_X1_Y11_N31 1 " "Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N31; Fanout = 1; REG Node = 'REG_TEMP\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "1.507 ns" { CE~clkctrl REG_TEMP[7] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.73 % ) " "Info: Total cell delay = 1.806 ns ( 64.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 35.27 % ) " "Info: Total interconnect delay = 0.984 ns ( 35.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[7] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.524 ns + Longest register pin " "Info: + Longest register to pin delay is 4.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_TEMP\[7\] 1 REG LCFF_X1_Y11_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y11_N31; Fanout = 1; REG Node = 'REG_TEMP\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { REG_TEMP[7] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.438 ns) + CELL(3.086 ns) 4.524 ns PC_OUT\[7\] 2 PIN PIN_36 0 " "Info: 2: + IC(1.438 ns) + CELL(3.086 ns) = 4.524 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'PC_OUT\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "4.524 ns" { REG_TEMP[7] PC_OUT[7] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.086 ns ( 68.21 % ) " "Info: Total cell delay = 3.086 ns ( 68.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.438 ns ( 31.79 % ) " "Info: Total interconnect delay = 1.438 ns ( 31.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "4.524 ns" { REG_TEMP[7] PC_OUT[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.524 ns" { REG_TEMP[7] PC_OUT[7] } { 0.000ns 1.438ns } { 0.000ns 3.086ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[7] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "4.524 ns" { REG_TEMP[7] PC_OUT[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.524 ns" { REG_TEMP[7] PC_OUT[7] } { 0.000ns 1.438ns } { 0.000ns 3.086ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CE PC_OUT\[14\] 6.243 ns Longest " "Info: Longest tpd from source pin \"CE\" to destination pin \"PC_OUT\[14\]\" is 6.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.725 ns) + CELL(3.378 ns) 6.243 ns PC_OUT\[14\] 2 PIN PIN_205 0 " "Info: 2: + IC(1.725 ns) + CELL(3.378 ns) = 6.243 ns; Loc. = PIN_205; Fanout = 0; PIN Node = 'PC_OUT\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "5.103 ns" { CE PC_OUT[14] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.518 ns ( 72.37 % ) " "Info: Total cell delay = 4.518 ns ( 72.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.725 ns ( 27.63 % ) " "Info: Total interconnect delay = 1.725 ns ( 27.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "6.243 ns" { CE PC_OUT[14] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.243 ns" { CE CE~combout PC_OUT[14] } { 0.000ns 0.000ns 1.725ns } { 0.000ns 1.140ns 3.378ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "REG_TEMP\[9\] PULSE_COUNT\[9\] CE -3.988 ns register " "Info: th for register \"REG_TEMP\[9\]\" (data pin = \"PULSE_COUNT\[9\]\", clock pin = \"CE\") is -3.988 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CE destination 2.790 ns + Longest register " "Info: + Longest clock path from clock \"CE\" to destination register is 2.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CE~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "0.143 ns" { CE CE~clkctrl } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(0.666 ns) 2.790 ns REG_TEMP\[9\] 3 REG LCFF_X1_Y11_N7 1 " "Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N7; Fanout = 1; REG Node = 'REG_TEMP\[9\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "1.507 ns" { CE~clkctrl REG_TEMP[9] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.73 % ) " "Info: Total cell delay = 1.806 ns ( 64.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 35.27 % ) " "Info: Total interconnect delay = 0.984 ns ( 35.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[9] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.084 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns PULSE_COUNT\[9\] 1 PIN PIN_4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_4; Fanout = 1; PIN Node = 'PULSE_COUNT\[9\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { PULSE_COUNT[9] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.601 ns) + CELL(0.370 ns) 6.976 ns REG_TEMP~219 2 COMB LCCOMB_X1_Y11_N6 1 " "Info: 2: + IC(5.601 ns) + CELL(0.370 ns) = 6.976 ns; Loc. = LCCOMB_X1_Y11_N6; Fanout = 1; COMB Node = 'REG_TEMP~219'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "5.971 ns" { PULSE_COUNT[9] REG_TEMP~219 } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.084 ns REG_TEMP\[9\] 3 REG LCFF_X1_Y11_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.084 ns; Loc. = LCFF_X1_Y11_N7; Fanout = 1; REG Node = 'REG_TEMP\[9\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "0.108 ns" { REG_TEMP~219 REG_TEMP[9] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.483 ns ( 20.93 % ) " "Info: Total cell delay = 1.483 ns ( 20.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.601 ns ( 79.07 % ) " "Info: Total interconnect delay = 5.601 ns ( 79.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "7.084 ns" { PULSE_COUNT[9] REG_TEMP~219 REG_TEMP[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.084 ns" { PULSE_COUNT[9] PULSE_COUNT[9]~combout REG_TEMP~219 REG_TEMP[9] } { 0.000ns 0.000ns 5.601ns 0.000ns } { 0.000ns 1.005ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[9] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "7.084 ns" { PULSE_COUNT[9] REG_TEMP~219 REG_TEMP[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.084 ns" { PULSE_COUNT[9] PULSE_COUNT[9]~combout REG_TEMP~219 REG_TEMP[9] } { 0.000ns 0.000ns 5.601ns 0.000ns } { 0.000ns 1.005ns 0.370ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 14 11:02:17 2006 " "Info: Processing ended: Wed Jun 14 11:02:17 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}