latch1.tan.qmsg

FPGA光电编码器输入模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 14 11:02:16 2006 " "Info: Processing started: Wed Jun 14 11:02:16 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off LATCH1 -c LATCH1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LATCH1 -c LATCH1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CE " "Info: Assuming node \"CE\" is an undefined clock" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CE " "Info: No valid register-to-register data paths exist for clock \"CE\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "REG_TEMP\[12\] CLR CE 5.381 ns register " "Info: tsu for register \"REG_TEMP\[12\]\" (data pin = \"CLR\", clock pin = \"CE\") is 5.381 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.211 ns + Longest pin register " "Info: + Longest pin to register delay is 8.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CLR 1 PIN PIN_58 16 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_58; Fanout = 16; PIN Node = 'CLR'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CLR } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.458 ns) + CELL(0.651 ns) 8.103 ns REG_TEMP~222 2 COMB LCCOMB_X1_Y11_N20 1 " "Info: 2: + IC(6.458 ns) + CELL(0.651 ns) = 8.103 ns; Loc. = LCCOMB_X1_Y11_N20; Fanout = 1; COMB Node = 'REG_TEMP~222'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "7.109 ns" { CLR REG_TEMP~222 } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.211 ns REG_TEMP\[12\] 3 REG LCFF_X1_Y11_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.211 ns; Loc. = LCFF_X1_Y11_N21; Fanout = 1; REG Node = 'REG_TEMP\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "0.108 ns" { REG_TEMP~222 REG_TEMP[12] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.753 ns ( 21.35 % ) " "Info: Total cell delay = 1.753 ns ( 21.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.458 ns ( 78.65 % ) " "Info: Total interconnect delay = 6.458 ns ( 78.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "8.211 ns" { CLR REG_TEMP~222 REG_TEMP[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.211 ns" { CLR CLR~combout REG_TEMP~222 REG_TEMP[12] } { 0.000ns 0.000ns 6.458ns 0.000ns } { 0.000ns 0.994ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CE destination 2.790 ns - Shortest register " "Info: - Shortest clock path from clock \"CE\" to destination register is 2.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "" { CE } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CE~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "0.143 ns" { CE CE~clkctrl } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(0.666 ns) 2.790 ns REG_TEMP\[12\] 3 REG LCFF_X1_Y11_N21 1 " "Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N21; Fanout = 1; REG Node = 'REG_TEMP\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "1.507 ns" { CE~clkctrl REG_TEMP[12] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/LATCH1/LATCH1.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.73 % ) " "Info: Total cell delay = 1.806 ns ( 64.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 35.27 % ) " "Info: Total interconnect delay = 0.984 ns ( 35.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[12] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "8.211 ns" { CLR REG_TEMP~222 REG_TEMP[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.211 ns" { CLR CLR~combout REG_TEMP~222 REG_TEMP[12] } { 0.000ns 0.000ns 6.458ns 0.000ns } { 0.000ns 0.994ns 0.651ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LATCH1" "UNKNOWN" "V1" "D:/altera/fpga+dsp/LATCH1/db/LATCH1.quartus_db" { Floorplan "D:/altera/fpga+dsp/LATCH1/" "" "2.790 ns" { CE CE~clkctrl REG_TEMP[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.790 ns" { CE CE~combout CE~clkctrl REG_TEMP[12] } { 0.000ns 0.000ns 0.143ns 0.841ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}