latch1.v

来自「FPGA光电编码器输入模块」· Verilog 代码 · 共 23 行

 module LATCH1(CLR,CE,PULSE_COUNT,PC_OUT);
  input CLR,CE;
  input [15:0]PULSE_COUNT;
  output [15:0] PC_OUT;
  reg [15:0] REG_TEMP;
  reg [15:0] PC_OUT;
  wire [15:0] PUSLE_COUNT;
  
  always @(posedge CE)
   begin 
      REG_TEMP<=PULSE_COUNT;
      if(CLR==1'b0)
        REG_TEMP<={16{1'b0}};
   end
  always @(CE)
    begin
       if(CE==1)
          PC_OUT<=REG_TEMP;
       else
          PC_OUT<={16{1'bz}};
     end
   //assign PC_OUT=REG_TEMP;
  endmodule