latch1.tan.summary

FPGA光电编码器输入模块

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.381 ns
From           : CLR
To             : REG_TEMP[12]
From Clock     : --
To Clock       : CE
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.618 ns
From           : REG_TEMP[7]
To             : PC_OUT[7]
From Clock     : CE
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.243 ns
From           : CE
To             : PC_OUT[14]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.988 ns
From           : PULSE_COUNT[9]
To             : REG_TEMP[9]
From Clock     : --
To Clock       : CE
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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