📄 latch1.tan.rpt
字号:
; N/A ; None ; 7.301 ns ; REG_TEMP[15] ; PC_OUT[15] ; CE ;
; N/A ; None ; 7.299 ns ; REG_TEMP[11] ; PC_OUT[11] ; CE ;
; N/A ; None ; 7.283 ns ; REG_TEMP[4] ; PC_OUT[4] ; CE ;
; N/A ; None ; 7.184 ns ; REG_TEMP[2] ; PC_OUT[2] ; CE ;
; N/A ; None ; 6.898 ns ; REG_TEMP[6] ; PC_OUT[6] ; CE ;
; N/A ; None ; 6.896 ns ; REG_TEMP[10] ; PC_OUT[10] ; CE ;
; N/A ; None ; 6.895 ns ; REG_TEMP[8] ; PC_OUT[8] ; CE ;
; N/A ; None ; 6.895 ns ; REG_TEMP[3] ; PC_OUT[3] ; CE ;
+-------+--------------+------------+--------------+------------+------------+
+-----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------------+
; N/A ; None ; 6.243 ns ; CE ; PC_OUT[14] ;
; N/A ; None ; 5.476 ns ; CE ; PC_OUT[15] ;
; N/A ; None ; 5.463 ns ; CE ; PC_OUT[13] ;
; N/A ; None ; 5.463 ns ; CE ; PC_OUT[11] ;
; N/A ; None ; 5.453 ns ; CE ; PC_OUT[4] ;
; N/A ; None ; 5.453 ns ; CE ; PC_OUT[2] ;
; N/A ; None ; 5.436 ns ; CE ; PC_OUT[8] ;
; N/A ; None ; 5.436 ns ; CE ; PC_OUT[6] ;
; N/A ; None ; 5.436 ns ; CE ; PC_OUT[3] ;
; N/A ; None ; 5.426 ns ; CE ; PC_OUT[10] ;
; N/A ; None ; 5.100 ns ; CE ; PC_OUT[9] ;
; N/A ; None ; 5.100 ns ; CE ; PC_OUT[7] ;
; N/A ; None ; 5.100 ns ; CE ; PC_OUT[1] ;
; N/A ; None ; 5.086 ns ; CE ; PC_OUT[12] ;
; N/A ; None ; 5.086 ns ; CE ; PC_OUT[5] ;
; N/A ; None ; 5.086 ns ; CE ; PC_OUT[0] ;
+-------+-------------------+-----------------+------+------------+
+-------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-----------------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-----------------+--------------+----------+
; N/A ; None ; -3.988 ns ; PULSE_COUNT[9] ; REG_TEMP[9] ; CE ;
; N/A ; None ; -4.066 ns ; PULSE_COUNT[0] ; REG_TEMP[0] ; CE ;
; N/A ; None ; -4.114 ns ; PULSE_COUNT[8] ; REG_TEMP[8] ; CE ;
; N/A ; None ; -4.254 ns ; PULSE_COUNT[13] ; REG_TEMP[13] ; CE ;
; N/A ; None ; -4.290 ns ; PULSE_COUNT[4] ; REG_TEMP[4] ; CE ;
; N/A ; None ; -4.291 ns ; PULSE_COUNT[7] ; REG_TEMP[7] ; CE ;
; N/A ; None ; -4.302 ns ; PULSE_COUNT[14] ; REG_TEMP[14] ; CE ;
; N/A ; None ; -4.452 ns ; PULSE_COUNT[2] ; REG_TEMP[2] ; CE ;
; N/A ; None ; -4.506 ns ; PULSE_COUNT[15] ; REG_TEMP[15] ; CE ;
; N/A ; None ; -4.613 ns ; PULSE_COUNT[11] ; REG_TEMP[11] ; CE ;
; N/A ; None ; -4.623 ns ; PULSE_COUNT[5] ; REG_TEMP[5] ; CE ;
; N/A ; None ; -4.626 ns ; PULSE_COUNT[1] ; REG_TEMP[1] ; CE ;
; N/A ; None ; -4.635 ns ; CLR ; REG_TEMP[0] ; CE ;
; N/A ; None ; -4.647 ns ; PULSE_COUNT[10] ; REG_TEMP[10] ; CE ;
; N/A ; None ; -4.814 ns ; PULSE_COUNT[12] ; REG_TEMP[12] ; CE ;
; N/A ; None ; -4.879 ns ; PULSE_COUNT[6] ; REG_TEMP[6] ; CE ;
; N/A ; None ; -5.034 ns ; PULSE_COUNT[3] ; REG_TEMP[3] ; CE ;
; N/A ; None ; -5.071 ns ; CLR ; REG_TEMP[6] ; CE ;
; N/A ; None ; -5.071 ns ; CLR ; REG_TEMP[11] ; CE ;
; N/A ; None ; -5.072 ns ; CLR ; REG_TEMP[5] ; CE ;
; N/A ; None ; -5.074 ns ; CLR ; REG_TEMP[7] ; CE ;
; N/A ; None ; -5.074 ns ; CLR ; REG_TEMP[15] ; CE ;
; N/A ; None ; -5.078 ns ; CLR ; REG_TEMP[1] ; CE ;
; N/A ; None ; -5.079 ns ; CLR ; REG_TEMP[13] ; CE ;
; N/A ; None ; -5.079 ns ; CLR ; REG_TEMP[14] ; CE ;
; N/A ; None ; -5.108 ns ; CLR ; REG_TEMP[8] ; CE ;
; N/A ; None ; -5.110 ns ; CLR ; REG_TEMP[2] ; CE ;
; N/A ; None ; -5.110 ns ; CLR ; REG_TEMP[4] ; CE ;
; N/A ; None ; -5.110 ns ; CLR ; REG_TEMP[9] ; CE ;
; N/A ; None ; -5.112 ns ; CLR ; REG_TEMP[3] ; CE ;
; N/A ; None ; -5.114 ns ; CLR ; REG_TEMP[10] ; CE ;
; N/A ; None ; -5.115 ns ; CLR ; REG_TEMP[12] ; CE ;
+---------------+-------------+-----------+-----------------+--------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Wed Jun 14 11:02:16 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LATCH1 -c LATCH1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CE" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CE"
Info: tsu for register "REG_TEMP[12]" (data pin = "CLR", clock pin = "CE") is 5.381 ns
Info: + Longest pin to register delay is 8.211 ns
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_58; Fanout = 16; PIN Node = 'CLR'
Info: 2: + IC(6.458 ns) + CELL(0.651 ns) = 8.103 ns; Loc. = LCCOMB_X1_Y11_N20; Fanout = 1; COMB Node = 'REG_TEMP~222'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.211 ns; Loc. = LCFF_X1_Y11_N21; Fanout = 1; REG Node = 'REG_TEMP[12]'
Info: Total cell delay = 1.753 ns ( 21.35 % )
Info: Total interconnect delay = 6.458 ns ( 78.65 % )
Info: + Micro setup delay of destination is -0.040 ns
Info: - Shortest clock path from clock "CE" to destination register is 2.790 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'
Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N21; Fanout = 1; REG Node = 'REG_TEMP[12]'
Info: Total cell delay = 1.806 ns ( 64.73 % )
Info: Total interconnect delay = 0.984 ns ( 35.27 % )
Info: tco from clock "CE" to destination pin "PC_OUT[7]" through register "REG_TEMP[7]" is 7.618 ns
Info: + Longest clock path from clock "CE" to source register is 2.790 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'
Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N31; Fanout = 1; REG Node = 'REG_TEMP[7]'
Info: Total cell delay = 1.806 ns ( 64.73 % )
Info: Total interconnect delay = 0.984 ns ( 35.27 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 4.524 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y11_N31; Fanout = 1; REG Node = 'REG_TEMP[7]'
Info: 2: + IC(1.438 ns) + CELL(3.086 ns) = 4.524 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'PC_OUT[7]'
Info: Total cell delay = 3.086 ns ( 68.21 % )
Info: Total interconnect delay = 1.438 ns ( 31.79 % )
Info: Longest tpd from source pin "CE" to destination pin "PC_OUT[14]" is 6.243 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
Info: 2: + IC(1.725 ns) + CELL(3.378 ns) = 6.243 ns; Loc. = PIN_205; Fanout = 0; PIN Node = 'PC_OUT[14]'
Info: Total cell delay = 4.518 ns ( 72.37 % )
Info: Total interconnect delay = 1.725 ns ( 27.63 % )
Info: th for register "REG_TEMP[9]" (data pin = "PULSE_COUNT[9]", clock pin = "CE") is -3.988 ns
Info: + Longest clock path from clock "CE" to destination register is 2.790 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'
Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X1_Y11_N7; Fanout = 1; REG Node = 'REG_TEMP[9]'
Info: Total cell delay = 1.806 ns ( 64.73 % )
Info: Total interconnect delay = 0.984 ns ( 35.27 % )
Info: + Micro hold delay of destination is 0.306 ns
Info: - Shortest pin to register delay is 7.084 ns
Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_4; Fanout = 1; PIN Node = 'PULSE_COUNT[9]'
Info: 2: + IC(5.601 ns) + CELL(0.370 ns) = 6.976 ns; Loc. = LCCOMB_X1_Y11_N6; Fanout = 1; COMB Node = 'REG_TEMP~219'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.084 ns; Loc. = LCFF_X1_Y11_N7; Fanout = 1; REG Node = 'REG_TEMP[9]'
Info: Total cell delay = 1.483 ns ( 20.93 % )
Info: Total interconnect delay = 5.601 ns ( 79.07 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Jun 14 11:02:17 2006
Info: Elapsed time: 00:00:02
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