📄 cfb_sp.fit.qmsg
字号:
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "21 21 " "Info: No exact pin location assignment(s) for 21 pins of 21 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[0\] " "Info: Pin PC_OUT\[0\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[1\] " "Info: Pin PC_OUT\[1\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[2\] " "Info: Pin PC_OUT\[2\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[3\] " "Info: Pin PC_OUT\[3\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[4\] " "Info: Pin PC_OUT\[4\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[5\] " "Info: Pin PC_OUT\[5\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[5] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[6\] " "Info: Pin PC_OUT\[6\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[7\] " "Info: Pin PC_OUT\[7\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[8\] " "Info: Pin PC_OUT\[8\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[9\] " "Info: Pin PC_OUT\[9\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[10\] " "Info: Pin PC_OUT\[10\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[11\] " "Info: Pin PC_OUT\[11\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[12\] " "Info: Pin PC_OUT\[12\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[13\] " "Info: Pin PC_OUT\[13\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[14\] " "Info: Pin PC_OUT\[14\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PC_OUT\[15\] " "Info: Pin PC_OUT\[15\] not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CE " "Info: Pin CE not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CE } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CE } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLR } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CLR } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "INB " "Info: Pin INB not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "INB" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { INB } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { INB } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "INA " "Info: Pin INA not assigned to an exact location on the device" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "INA" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { INA } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { INA } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CE (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CE (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[15\] " "Info: Destination node PC_OUT\[15\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[15] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[14\] " "Info: Destination node PC_OUT\[14\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[14] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[13\] " "Info: Destination node PC_OUT\[13\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[13] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[12\] " "Info: Destination node PC_OUT\[12\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[12] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[11\] " "Info: Destination node PC_OUT\[11\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[11] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[10\] " "Info: Destination node PC_OUT\[10\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[10] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[9\] " "Info: Destination node PC_OUT\[9\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[9] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[8\] " "Info: Destination node PC_OUT\[8\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[8] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[7\] " "Info: Destination node PC_OUT\[7\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[7] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PC_OUT\[6\] " "Info: Destination node PC_OUT\[6\]" { } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PC_OUT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PC_OUT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PC_OUT[6] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CE } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CE } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN 24 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node CLK (placed in PIN 24 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CLK } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "F4:F4\|inst1 " "Info: Automatically promoted node F4:F4\|inst1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst1" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { F4:F4|inst1 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { F4:F4|inst1 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLR (placed in PIN 27 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node CLR (placed in PIN 27 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\] " "Info: Destination node PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\]" { } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LATCH1:LATCH1\|REG_TEMP~210 " "Info: Destination node LATCH1:LATCH1\|REG_TEMP~210" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LATCH1:LATCH1\|REG_TEMP~210" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP~210 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { LATCH1:LATCH1|REG_TEMP~210 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\] " "Info: Destination node PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]" { } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LATCH1:LATCH1\|REG_TEMP~211 " "Info: Destination node LATCH1:LATCH1\|REG_TEMP~211" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LATCH1:LATCH1\|REG_TEMP~211" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP~211 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { LATCH1:LATCH1|REG_TEMP~211 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[2\] " "Info: Destination node PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[2\]" { } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LATCH1:LATCH1\|REG_TEMP~212 " "Info: Destination node LATCH1:LATCH1\|REG_TEMP~212" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LATCH1:LATCH1\|REG_TEMP~212" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP~212 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { LATCH1:LATCH1|REG_TEMP~212 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[3\] " "Info: Destination node PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[3\]" { } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LATCH1:LATCH1\|REG_TEMP~213 " "Info: Destination node LATCH1:LATCH1\|REG_TEMP~213" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LATCH1:LATCH1\|REG_TEMP~213" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP~213 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { LATCH1:LATCH1|REG_TEMP~213 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[4\] " "Info: Destination node PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[4\]" { } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LATCH1:LATCH1\|REG_TEMP~214 " "Info: Destination node LATCH1:LATCH1\|REG_TEMP~214" { } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LATCH1:LATCH1\|REG_TEMP~214" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP~214 } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { LATCH1:LATCH1|REG_TEMP~214 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLR } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" { Floorplan "D:/altera/fpga+dsp/CFB_SP/CFB_SP.fld" "" "" { CLR } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" { } { } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
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