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📄 cfb_sp.sim.vwf

📁 FPGA光电编码器输入模块
💻 VWF
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123 
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TRANSITION_LIST("PC_OUT[3]")
{
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TRANSITION_LIST("PC_OUT[2]")
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TRANSITION_LIST("PC_OUT[1]")
{
	NODE
	{
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TRANSITION_LIST("PC_OUT[0]")
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}

DISPLAY_LINE
{
	CHANNEL = "CLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "CLR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "INA";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "INB";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "CE";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
	CHILDREN = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "PC_OUT[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 5;
}

TIME_BAR
{
	TIME = 12325;
	MASTER = TRUE;
}
;
123

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