cfb_sp.map.qmsg

FPGA光电编码器输入模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 14 15:14:28 2006 " "Info: Processing started: Wed Jun 14 15:14:28 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CFB_SP -c CFB_SP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CFB_SP -c CFB_SP" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_count.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pulse_count.v" { { "Info" "ISGN_ENTITY_NAME" "1 PULSE_COUNT " "Info: Found entity 1: PULSE_COUNT" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "F4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file F4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 F4 " "Info: Found entity 1: F4" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CFB_SP.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CFB_SP.v" { { "Info" "ISGN_ENTITY_NAME" "1 CFB_SP " "Info: Found entity 1: CFB_SP" {  } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LATCH1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LATCH1.v" { { "Info" "ISGN_ENTITY_NAME" "1 LATCH1 " "Info: Found entity 1: LATCH1" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CFB_SP " "Info: Elaborating entity \"CFB_SP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "F4 F4:F4 " "Info: Elaborating entity \"F4\" for hierarchy \"F4:F4\"" {  } { { "CFB_SP.v" "F4" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 16 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PULSE_COUNT PULSE_COUNT:PULSE_COUNT " "Info: Elaborating entity \"PULSE_COUNT\" for hierarchy \"PULSE_COUNT:PULSE_COUNT\"" {  } { { "CFB_SP.v" "PULSE_COUNT" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 24 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 pulse_count.v(11) " "Warning (10230): Verilog HDL assignment warning at pulse_count.v(11): truncated value with size 32 to match size of target (16)" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 pulse_count.v(13) " "Warning (10230): Verilog HDL assignment warning at pulse_count.v(13): truncated value with size 32 to match size of target (16)" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LATCH1 LATCH1:LATCH1 " "Info: Elaborating entity \"LATCH1\" for hierarchy \"LATCH1:LATCH1\"" {  } { { "CFB_SP.v" "LATCH1" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 28 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "PUSLE_COUNT LATCH1.v(8) " "Info (10035): Verilog HDL or VHDL information at LATCH1.v(8): object \"PUSLE_COUNT\" declared but not used" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 8 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "17 16 LATCH1.v(14) " "Warning (10230): Verilog HDL assignment warning at LATCH1.v(14): truncated value with size 17 to match size of target (16)" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "REG_TEMP LATCH1.v(19) " "Warning (10235): Verilog HDL Always Construct warning at LATCH1.v(19): variable \"REG_TEMP\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 19 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "61 " "Info: Implemented 61 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "40 " "Info: Implemented 40 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 14 15:14:36 2006 " "Info: Processing ended: Wed Jun 14 15:14:36 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}