cfb_sp.hif

FPGA光电编码器输入模块

Version 5.1 Build 176 10/26/2005 SJ Web Edition
10
727
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
F4
# storage
db|CFB_SP.(1).cnf
db|CFB_SP.(1).cnf
# case_insensitive
# source_file
F4.bdf
517f629535acba288012d1b522b0ea52
23
# hierarchies {
F4:F4
}
# end
# entity
CFB_SP
# storage
db|CFB_SP.(0).cnf
db|CFB_SP.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
CFB_SP.v
812d826cf2d29055ee4cbf2a113eaa0
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
pulse_count.v
d5d42d288055c7b86ebcf92c8696927b
}
# hierarchies {
|
}
# end
# entity
PULSE_COUNT
# storage
db|CFB_SP.(2).cnf
db|CFB_SP.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pulse_count.v
d5d42d288055c7b86ebcf92c8696927b
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
PULSE_COUNT:PULSE_COUNT
}
# end
# entity
LATCH1
# storage
db|CFB_SP.(3).cnf
db|CFB_SP.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LATCH1.v
f1fb2b8baf175d60e2a9291a64239ce
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
pulse_count.v
d5d42d288055c7b86ebcf92c8696927b
}
# hierarchies {
LATCH1:LATCH1
}
# end
# complete