cfb_sp.v

来自「FPGA光电编码器输入模块」· Verilog 代码 · 共 34 行

 
`define count_reg_num 16
module CFB_SP(CLR,INA,INB,CE,CLK,PC_OUT);
  input CLR;
  input INA;
  input INB;
  input CLK;
  input CE;
  output [`count_reg_num-1:0] PC_OUT;
  //output [count_reg_num:0] COUNT;
 // reg [15:0] COUNT;
  reg F4_CLK;
  wire [`count_reg_num-1:0] COUNT;
  reg ENADD;
//parameter count_reg_num=15;
  F4 F4(
	.INA(INA),
	.INB(INB),
	.CLR(CLR),
	.CLK(CLK),
	.ENADD(ENADD),
	.F4_CLK(F4_CLK)
  );
 PULSE_COUNT PULSE_COUNT(.F4_CLK(F4_CLK),
 .RESET(CLR),
 .DIRECTION(ENADD),
 .PULSE_COUNT(COUNT));
LATCH1 LATCH1(.CLR(CLR),
             .CE(CE),
             .PULSE_COUNT(COUNT),
             .PC_OUT(PC_OUT));
//LATCH LATCH(CLR,CE,COUNT,PC_OUT);          
            
endmodule