cfb_sp.map.rpt

FPGA光电编码器输入模块

+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+
; pulse_count.v                    ; yes             ; User Verilog HDL File              ; D:/altera/fpga+dsp/CFB_SP/pulse_count.v ;
; F4.bdf                           ; yes             ; User Block Diagram/Schematic File  ; D:/altera/fpga+dsp/CFB_SP/F4.bdf        ;
; CFB_SP.v                         ; yes             ; User Verilog HDL File              ; D:/altera/fpga+dsp/CFB_SP/CFB_SP.v      ;
; LATCH1.v                         ; yes             ; User Verilog HDL File              ; D:/altera/fpga+dsp/CFB_SP/LATCH1.v      ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 36    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 15    ;
;     -- <=2 input functions                  ; 18    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 21    ;
;     -- arithmetic mode                      ; 15    ;
; Total registers                             ; 36    ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; CLR   ;
; Maximum fan-out                             ; 36    ;
; Total fan-out                               ; 217   ;
; Average fan-out                             ; 2.33  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                        ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+
; Compilation Hierarchy Node   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name             ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+
; |CFB_SP                      ; 36 (0)            ; 36 (0)       ; 0           ; 0            ; 0       ; 0         ; 21   ; 0            ; |CFB_SP                         ;
;    |F4:F4|                   ; 4 (4)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |CFB_SP|F4:F4                   ;
;    |LATCH1:LATCH1|           ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |CFB_SP|LATCH1:LATCH1           ;
;    |PULSE_COUNT:PULSE_COUNT| ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |CFB_SP|PULSE_COUNT:PULSE_COUNT ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; F4:F4|inst26~0                                         ;   ;
; Number of logic cells representing combinational loops ; 1 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 36    ;
; Number of registers using Synchronous Clear  ; 16    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/fpga+dsp/CFB_SP/CFB_SP.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Wed Jun 14 15:14:28 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CFB_SP -c CFB_SP
Info: Found 1 design units, including 1 entities, in source file pulse_count.v
    Info: Found entity 1: PULSE_COUNT
Info: Found 1 design units, including 1 entities, in source file F4.bdf
    Info: Found entity 1: F4
Info: Found 1 design units, including 1 entities, in source file CFB_SP.v
    Info: Found entity 1: CFB_SP
Info: Found 1 design units, including 1 entities, in source file LATCH1.v
    Info: Found entity 1: LATCH1
Info: Elaborating entity "CFB_SP" for the top level hierarchy
Info: Elaborating entity "F4" for hierarchy "F4:F4"
Info: Elaborating entity "PULSE_COUNT" for hierarchy "PULSE_COUNT:PULSE_COUNT"
Warning (10230): Verilog HDL assignment warning at pulse_count.v(11): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at pulse_count.v(13): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "LATCH1" for hierarchy "LATCH1:LATCH1"
Info (10035): Verilog HDL or VHDL information at LATCH1.v(8): object "PUSLE_COUNT" declared but not used
Warning (10230): Verilog HDL assignment warning at LATCH1.v(14): truncated value with size 17 to match size of target (16)
Warning (10235): Verilog HDL Always Construct warning at LATCH1.v(19): variable "REG_TEMP" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Implemented 61 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 16 output pins
    Info: Implemented 40 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Wed Jun 14 15:14:36 2006
    Info: Elapsed time: 00:00:10