cfb_sp.tan.rpt

FPGA光电编码器输入模块

    Warning: Node "F4:F4|inst26" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CE" is an undefined clock
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "F4:F4|inst" as buffer
    Info: Detected ripple clock "F4:F4|inst4" as buffer
    Info: Detected ripple clock "F4:F4|inst5" as buffer
    Info: Detected ripple clock "F4:F4|inst6" as buffer
    Info: Detected gated clock "F4:F4|inst1" as buffer
Info: No valid register-to-register data paths exist for clock "CE"
Info: Clock "CLK" has Internal fmax of 237.36 MHz between source register "PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]" and destination register "PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]" (period= 4.213 ns)
    Info: + Longest register to register delay is 3.224 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y8_N3; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]'
        Info: 2: + IC(0.767 ns) + CELL(0.621 ns) = 1.388 ns; Loc. = LCCOMB_X2_Y8_N2; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.474 ns; Loc. = LCCOMB_X2_Y8_N4; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.560 ns; Loc. = LCCOMB_X2_Y8_N6; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.646 ns; Loc. = LCCOMB_X2_Y8_N8; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.732 ns; Loc. = LCCOMB_X2_Y8_N10; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.818 ns; Loc. = LCCOMB_X2_Y8_N12; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255'
        Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 2.008 ns; Loc. = LCCOMB_X2_Y8_N14; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257'
        Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.094 ns; Loc. = LCCOMB_X2_Y8_N16; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.180 ns; Loc. = LCCOMB_X2_Y8_N18; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.266 ns; Loc. = LCCOMB_X2_Y8_N20; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.352 ns; Loc. = LCCOMB_X2_Y8_N22; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.438 ns; Loc. = LCCOMB_X2_Y8_N24; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.524 ns; Loc. = LCCOMB_X2_Y8_N26; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.610 ns; Loc. = LCCOMB_X2_Y8_N28; Fanout = 1; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271'
        Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 3.116 ns; Loc. = LCCOMB_X2_Y8_N30; Fanout = 1; COMB Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272'
        Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 3.224 ns; Loc. = LCFF_X2_Y8_N31; Fanout = 2; REG Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]'
        Info: Total cell delay = 2.457 ns ( 76.21 % )
        Info: Total interconnect delay = 0.767 ns ( 23.79 % )
    Info: - Smallest clock skew is -0.725 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 5.797 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4|inst4'
            Info: 4: + IC(0.000 ns) + CELL(0.393 ns) = 3.503 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4|inst1'
            Info: 5: + IC(0.738 ns) + CELL(0.000 ns) = 4.241 ns; Loc. = CLKCTRL_G0; Fanout = 16; COMB Node = 'F4:F4|inst1~clkctrl'
            Info: 6: + IC(0.890 ns) + CELL(0.666 ns) = 5.797 ns; Loc. = LCFF_X2_Y8_N31; Fanout = 2; REG Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]'
            Info: Total cell delay = 3.159 ns ( 54.49 % )
            Info: Total interconnect delay = 2.638 ns ( 45.51 % )
        Info: - Longest clock path from clock "CLK" to source register is 6.522 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 3; REG Node = 'F4:F4|inst6'
            Info: 4: + IC(0.467 ns) + CELL(0.651 ns) = 4.228 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4|inst1'
            Info: 5: + IC(0.738 ns) + CELL(0.000 ns) = 4.966 ns; Loc. = CLKCTRL_G0; Fanout = 16; COMB Node = 'F4:F4|inst1~clkctrl'
            Info: 6: + IC(0.890 ns) + CELL(0.666 ns) = 6.522 ns; Loc. = LCFF_X2_Y8_N3; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]'
            Info: Total cell delay = 3.417 ns ( 52.39 % )
            Info: Total interconnect delay = 3.105 ns ( 47.61 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "F4:F4|inst4" (data pin = "INB", clock pin = "CLK") is 4.575 ns
    Info: + Longest pin to register delay is 7.421 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_6; Fanout = 1; PIN Node = 'INB'
        Info: 2: + IC(5.966 ns) + CELL(0.460 ns) = 7.421 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4|inst4'
        Info: Total cell delay = 1.455 ns ( 19.61 % )
        Info: Total interconnect delay = 5.966 ns ( 80.39 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.806 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.806 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4|inst4'
        Info: Total cell delay = 1.796 ns ( 64.01 % )
        Info: Total interconnect delay = 1.010 ns ( 35.99 % )
Info: tco from clock "CE" to destination pin "PC_OUT[4]" through register "LATCH1:LATCH1|REG_TEMP[4]" is 7.778 ns
    Info: + Longest clock path from clock "CE" to source register is 2.825 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'
        Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.825 ns; Loc. = LCFF_X1_Y8_N1; Fanout = 1; REG Node = 'LATCH1:LATCH1|REG_TEMP[4]'
        Info: Total cell delay = 1.796 ns ( 63.58 % )
        Info: Total interconnect delay = 1.029 ns ( 36.42 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.649 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N1; Fanout = 1; REG Node = 'LATCH1:LATCH1|REG_TEMP[4]'
        Info: 2: + IC(1.553 ns) + CELL(3.096 ns) = 4.649 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'PC_OUT[4]'
        Info: Total cell delay = 3.096 ns ( 66.59 % )
        Info: Total interconnect delay = 1.553 ns ( 33.41 % )
Info: Longest tpd from source pin "CE" to destination pin "PC_OUT[10]" is 5.560 ns
    Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'
    Info: 2: + IC(1.295 ns) + CELL(3.135 ns) = 5.560 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'PC_OUT[10]'
    Info: Total cell delay = 4.265 ns ( 76.71 % )
    Info: Total interconnect delay = 1.295 ns ( 23.29 % )
Info: th for register "PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0]" (data pin = "CLR", clock pin = "CLK") is 3.759 ns
    Info: + Longest clock path from clock "CLK" to destination register is 6.522 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 3; REG Node = 'F4:F4|inst6'
        Info: 4: + IC(0.467 ns) + CELL(0.651 ns) = 4.228 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4|inst1'
        Info: 5: +