pulse_count.v

来自「FPGA光电编码器输入模块」· Verilog 代码 · 共 19 行

 `define count_reg_num 16
module PULSE_COUNT(F4_CLK,RESET,DIRECTION,PULSE_COUNT);
   input F4_CLK,RESET,DIRECTION;
   output [`count_reg_num-1:0] PULSE_COUNT;
   reg [`count_reg_num-1:0] PULSE_COUNT;
   always @(posedge F4_CLK)
     begin
      if(RESET==1'b1)
       begin 
        if(DIRECTION==1'b1)
         PULSE_COUNT<=PULSE_COUNT+1;
        else
         PULSE_COUNT<=PULSE_COUNT-1;
       end
      else
        PULSE_COUNT<=0;
     end 
 endmodule