f4.v

FPGA光电编码器输入模块

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module F4(
	INA,
	INB,
	CLR,
	CLK,
	ENADD,
	F4_CLK
);

input	INA;
input	INB;
input	CLR;
input	CLK;
output	ENADD;
output	F4_CLK;

wire	SYNTHESIZED_WIRE_26;
wire	SYNTHESIZED_WIRE_27;
wire	SYNTHESIZED_WIRE_28;
reg	SYNTHESIZED_WIRE_29;
wire	SYNTHESIZED_WIRE_30;
reg	SYNTHESIZED_WIRE_31;
reg	SYNTHESIZED_WIRE_32;
wire	SYNTHESIZED_WIRE_33;
wire	SYNTHESIZED_WIRE_34;
reg	SYNTHESIZED_WIRE_35;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;
wire	SYNTHESIZED_WIRE_12;
wire	SYNTHESIZED_WIRE_13;
wire	SYNTHESIZED_WIRE_14;
wire	SYNTHESIZED_WIRE_15;
wire	SYNTHESIZED_WIRE_16;
wire	SYNTHESIZED_WIRE_17;
wire	SYNTHESIZED_WIRE_18;
wire	SYNTHESIZED_WIRE_20;

assign	ENADD = SYNTHESIZED_WIRE_20;




always@(posedge CLK or negedge CLR)
begin
if (!CLR)
	begin
	SYNTHESIZED_WIRE_31 <= 0;
	end
else
	begin
	SYNTHESIZED_WIRE_31 <= INA;
	end
end
assign	F4_CLK = SYNTHESIZED_WIRE_26 & SYNTHESIZED_WIRE_27;
assign	SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_28 & SYNTHESIZED_WIRE_29 & SYNTHESIZED_WIRE_30;
assign	SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_32 & SYNTHESIZED_WIRE_33;
assign	SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_28 & SYNTHESIZED_WIRE_32 & SYNTHESIZED_WIRE_34;
assign	SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_28 & SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_35;
assign	SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_29;
assign	SYNTHESIZED_WIRE_28 =  ~SYNTHESIZED_WIRE_31;
assign	SYNTHESIZED_WIRE_30 =  ~SYNTHESIZED_WIRE_32;
assign	SYNTHESIZED_WIRE_33 =  ~SYNTHESIZED_WIRE_35;
assign	SYNTHESIZED_WIRE_34 =  ~SYNTHESIZED_WIRE_29;
assign	SYNTHESIZED_WIRE_26 = ~(SYNTHESIZED_WIRE_10 | SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13);
assign	SYNTHESIZED_WIRE_27 = ~(SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17);
assign	SYNTHESIZED_WIRE_20 = ~(SYNTHESIZED_WIRE_18 & SYNTHESIZED_WIRE_26);
assign	SYNTHESIZED_WIRE_18 = ~(SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_27);

always@(posedge CLK or negedge CLR)
begin
if (!CLR)
	begin
	SYNTHESIZED_WIRE_32 <= 0;
	end
else
	begin
	SYNTHESIZED_WIRE_32 <= INB;
	end
end

always@(posedge CLK or negedge CLR)
begin
if (!CLR)
	begin
	SYNTHESIZED_WIRE_35 <= 0;
	end
else
	begin
	SYNTHESIZED_WIRE_35 <= SYNTHESIZED_WIRE_31;
	end
end

always@(posedge CLK or negedge CLR)
begin
if (!CLR)
	begin
	SYNTHESIZED_WIRE_29 <= 0;
	end
else
	begin
	SYNTHESIZED_WIRE_29 <= SYNTHESIZED_WIRE_32;
	end
end
assign	SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_33 & SYNTHESIZED_WIRE_30;
assign	SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_32;
assign	SYNTHESIZED_WIRE_11 = SYNTHESIZED_WIRE_28 & SYNTHESIZED_WIRE_35 & SYNTHESIZED_WIRE_32;


endmodule