code_fd.fit.qmsg

FPGA光电编码器输入模块

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C8Q208C8 " "Warning: Timing characteristics of device EP2C8Q208C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "16 " "Warning: Found 16 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[15\] 0 " "Warning: Pin \"PULSE_COUNT\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[14\] 0 " "Warning: Pin \"PULSE_COUNT\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[13\] 0 " "Warning: Pin \"PULSE_COUNT\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[12\] 0 " "Warning: Pin \"PULSE_COUNT\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[11\] 0 " "Warning: Pin \"PULSE_COUNT\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[10\] 0 " "Warning: Pin \"PULSE_COUNT\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[9\] 0 " "Warning: Pin \"PULSE_COUNT\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[8\] 0 " "Warning: Pin \"PULSE_COUNT\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[7\] 0 " "Warning: Pin \"PULSE_COUNT\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[6\] 0 " "Warning: Pin \"PULSE_COUNT\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[5\] 0 " "Warning: Pin \"PULSE_COUNT\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[4\] 0 " "Warning: Pin \"PULSE_COUNT\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[3\] 0 " "Warning: Pin \"PULSE_COUNT\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[2\] 0 " "Warning: Pin \"PULSE_COUNT\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[1\] 0 " "Warning: Pin \"PULSE_COUNT\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "PULSE_COUNT\[0\] 0 " "Warning: Pin \"PULSE_COUNT\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "16 " "Warning: Following 16 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[15\] GND " "Info: Pin PULSE_COUNT\[15\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[14\] GND " "Info: Pin PULSE_COUNT\[14\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[13\] GND " "Info: Pin PULSE_COUNT\[13\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[12\] GND " "Info: Pin PULSE_COUNT\[12\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[11\] GND " "Info: Pin PULSE_COUNT\[11\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[10\] GND " "Info: Pin PULSE_COUNT\[10\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[9\] GND " "Info: Pin PULSE_COUNT\[9\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[8\] GND " "Info: Pin PULSE_COUNT\[8\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[7\] GND " "Info: Pin PULSE_COUNT\[7\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[6\] GND " "Info: Pin PULSE_COUNT\[6\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[5\] GND " "Info: Pin PULSE_COUNT\[5\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[5] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[4\] GND " "Info: Pin PULSE_COUNT\[4\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[3\] GND " "Info: Pin PULSE_COUNT\[3\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[2\] GND " "Info: Pin PULSE_COUNT\[2\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[1\] GND " "Info: Pin PULSE_COUNT\[1\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PULSE_COUNT\[0\] GND " "Info: Pin PULSE_COUNT\[0\] has GND driving its datain port" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Code_FD" "UNKNOWN" "V1" "D:/altera/fpga+dsp/Code_FD/db/Code_FD.quartus_db" { Floorplan "D:/altera/fpga+dsp/Code_FD/" "" "" { PULSE_COUNT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" { Floorplan "D:/altera/fpga+dsp/Code_FD/Code_FD.fld" "" "" { PULSE_COUNT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 19 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 17:11:07 2006 " "Info: Processing ended: Tue Jun 13 17:11:07 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:48 " "Info: Elapsed time: 00:00:48" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}