code_fd.hier_info

FPGA光电编码器输入模块

|Code_FD
PULSE_COUNT[0] <= pulse_count:inst2.PULSE_COUNT[0]
PULSE_COUNT[1] <= pulse_count:inst2.PULSE_COUNT[1]
PULSE_COUNT[2] <= pulse_count:inst2.PULSE_COUNT[2]
PULSE_COUNT[3] <= pulse_count:inst2.PULSE_COUNT[3]
PULSE_COUNT[4] <= pulse_count:inst2.PULSE_COUNT[4]
PULSE_COUNT[5] <= pulse_count:inst2.PULSE_COUNT[5]
PULSE_COUNT[6] <= pulse_count:inst2.PULSE_COUNT[6]
PULSE_COUNT[7] <= pulse_count:inst2.PULSE_COUNT[7]
PULSE_COUNT[8] <= pulse_count:inst2.PULSE_COUNT[8]
PULSE_COUNT[9] <= pulse_count:inst2.PULSE_COUNT[9]
PULSE_COUNT[10] <= pulse_count:inst2.PULSE_COUNT[10]
PULSE_COUNT[11] <= pulse_count:inst2.PULSE_COUNT[11]
PULSE_COUNT[12] <= pulse_count:inst2.PULSE_COUNT[12]
PULSE_COUNT[13] <= pulse_count:inst2.PULSE_COUNT[13]
PULSE_COUNT[14] <= pulse_count:inst2.PULSE_COUNT[14]
PULSE_COUNT[15] <= pulse_count:inst2.PULSE_COUNT[15]
INA => F4:inst1.INA
CLR => F4:inst1.CLR
CLR => inst3.IN0
INB => F4:inst1.INB
CLK => F4:inst1.CLK


|Code_FD|pulse_count:inst2
F4_CLK => PULSE_COUNT[14]~reg0.CLK
F4_CLK => PULSE_COUNT[13]~reg0.CLK
F4_CLK => PULSE_COUNT[12]~reg0.CLK
F4_CLK => PULSE_COUNT[11]~reg0.CLK
F4_CLK => PULSE_COUNT[10]~reg0.CLK
F4_CLK => PULSE_COUNT[9]~reg0.CLK
F4_CLK => PULSE_COUNT[8]~reg0.CLK
F4_CLK => PULSE_COUNT[7]~reg0.CLK
F4_CLK => PULSE_COUNT[6]~reg0.CLK
F4_CLK => PULSE_COUNT[5]~reg0.CLK
F4_CLK => PULSE_COUNT[4]~reg0.CLK
F4_CLK => PULSE_COUNT[3]~reg0.CLK
F4_CLK => PULSE_COUNT[2]~reg0.CLK
F4_CLK => PULSE_COUNT[1]~reg0.CLK
F4_CLK => PULSE_COUNT[0]~reg0.CLK
F4_CLK => PULSE_COUNT[15]~reg0.CLK
RESET => PULSE_COUNT~16.OUTPUTSELECT
RESET => PULSE_COUNT~17.OUTPUTSELECT
RESET => PULSE_COUNT~18.OUTPUTSELECT
RESET => PULSE_COUNT~19.OUTPUTSELECT
RESET => PULSE_COUNT~20.OUTPUTSELECT
RESET => PULSE_COUNT~21.OUTPUTSELECT
RESET => PULSE_COUNT~22.OUTPUTSELECT
RESET => PULSE_COUNT~23.OUTPUTSELECT
RESET => PULSE_COUNT~24.OUTPUTSELECT
RESET => PULSE_COUNT~25.OUTPUTSELECT
RESET => PULSE_COUNT~26.OUTPUTSELECT
RESET => PULSE_COUNT~27.OUTPUTSELECT
RESET => PULSE_COUNT~28.OUTPUTSELECT
RESET => PULSE_COUNT~29.OUTPUTSELECT
RESET => PULSE_COUNT~30.OUTPUTSELECT
RESET => PULSE_COUNT~31.OUTPUTSELECT
DIRECTION => PULSE_COUNT~0.OUTPUTSELECT
DIRECTION => PULSE_COUNT~1.OUTPUTSELECT
DIRECTION => PULSE_COUNT~2.OUTPUTSELECT
DIRECTION => PULSE_COUNT~3.OUTPUTSELECT
DIRECTION => PULSE_COUNT~4.OUTPUTSELECT
DIRECTION => PULSE_COUNT~5.OUTPUTSELECT
DIRECTION => PULSE_COUNT~6.OUTPUTSELECT
DIRECTION => PULSE_COUNT~7.OUTPUTSELECT
DIRECTION => PULSE_COUNT~8.OUTPUTSELECT
DIRECTION => PULSE_COUNT~9.OUTPUTSELECT
DIRECTION => PULSE_COUNT~10.OUTPUTSELECT
DIRECTION => PULSE_COUNT~11.OUTPUTSELECT
DIRECTION => PULSE_COUNT~12.OUTPUTSELECT
DIRECTION => PULSE_COUNT~13.OUTPUTSELECT
DIRECTION => PULSE_COUNT~14.OUTPUTSELECT
DIRECTION => PULSE_COUNT~15.OUTPUTSELECT
PULSE_COUNT[0] <= PULSE_COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[1] <= PULSE_COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[2] <= PULSE_COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[3] <= PULSE_COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[4] <= PULSE_COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[5] <= PULSE_COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[6] <= PULSE_COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[7] <= PULSE_COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[8] <= PULSE_COUNT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[9] <= PULSE_COUNT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[10] <= PULSE_COUNT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[11] <= PULSE_COUNT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[12] <= PULSE_COUNT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[13] <= PULSE_COUNT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[14] <= PULSE_COUNT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PULSE_COUNT[15] <= PULSE_COUNT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Code_FD|F4:inst1
INA => ~NO_FANOUT~
CLR => ~NO_FANOUT~
INB => ~NO_FANOUT~
CLK => ~NO_FANOUT~
F4_CLK <= <GND>
ENADD <= <GND>