code_fd.v

来自「FPGA光电编码器输入模块」· Verilog 代码 · 共 50 行

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module Code_FD(
	CE,
	CLR,
	INA,
	INB,
	CLK,
	PC_OUT
);

input	CE;
input	CLR;
input	INA;
input	INB;
input	CLK;
output	[15:0] PC_OUT;

wire	[15:0] SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;





F4	b2v_inst(.INA(INA),
.CLR(CLR),.INB(INB),.CLK(CLK),.F4_CLK(SYNTHESIZED_WIRE_1),.ENADD(SYNTHESIZED_WIRE_2));

LATCH1	b2v_inst1(.CLR(CLR),
.CE(CE),.PULSE_COUNT(SYNTHESIZED_WIRE_0),.PC_OUT(PC_OUT));

pulse_count	b2v_inst2(.F4_CLK(SYNTHESIZED_WIRE_1),
.RESET(CLR),.DIRECTION(SYNTHESIZED_WIRE_2),.PULSE_COUNT(SYNTHESIZED_WIRE_0));


endmodule