code_fd.fit.summary

FPGA光电编码器输入模块

Fitter Status : Successful - Tue Jun 13 17:11:07 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : Code_FD
Top-level Entity Name : Code_FD
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Preliminary
Total logic elements : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 20 / 138 ( 14 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )