f4.v

来自「FPGA光电编码器输入模块」· Verilog 代码 · 共 44 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 5.1 (Build Build 176 10/26/2005)
// Created on Wed Jun 07 22:50:04 2006

//  Module Declaration
module F4
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	INA, CLR, INB, CLK, F4_CLK, ENADD
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input INA;
	input CLR;
	input INB;
	input CLK;
	output F4_CLK;
	output ENADD;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!



endmodule