code_fd.map.rpt

FPGA光电编码器输入模块

;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 20    ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |Code_FD                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |Code_FD            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/fpga+dsp/Code_FD/Code_FD.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Jun 13 17:10:06 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Code_FD -c Code_FD
Info: Found 1 design units, including 1 entities, in source file pulse_count.v
    Info: Found entity 1: pulse_count
Info: Found 1 design units, including 1 entities, in source file Code_FD.bdf
    Info: Found entity 1: Code_FD
Info: Elaborating entity "Code_FD" for the top level hierarchy
Info: Elaborating entity "pulse_count" for hierarchy "pulse_count:inst2"
Warning (10230): Verilog HDL assignment warning at pulse_count.v(10): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at pulse_count.v(12): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at pulse_count.v(15): truncated value with size 24 to match size of target (16)
Warning: Using design file F4.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: F4
Warning: Found the following files while searching for definition of entity "F4", but did not use these files because already using a different file containing the entity definition
    Warning: File: F4.bdf
Info: Elaborating entity "F4" for hierarchy "F4:inst1"
Info (10035): Verilog HDL or VHDL information at F4.v(33): object "INA" declared but not used
Info (10035): Verilog HDL or VHDL information at F4.v(34): object "CLR" declared but not used
Info (10035): Verilog HDL or VHDL information at F4.v(35): object "INB" declared but not used
Info (10035): Verilog HDL or VHDL information at F4.v(36): object "CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at F4.v(37): object "F4_CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at F4.v(38): object "ENADD" declared but not used
Warning (10034): Output port "F4_CLK" at F4.v(37) has no driver
Warning (10034): Output port "ENADD" at F4.v(38) has no driver
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[14]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[14]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[13]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[13]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[12]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[12]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[11]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[11]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[10]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[10]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[9]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[9]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[8]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[8]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[7]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[7]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[6]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[6]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[5]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[5]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[4]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[4]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[3]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[3]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[2]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[2]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[1]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[1]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[0]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[0]" with stuck clock port to stuck value GND
Warning: No clock transition on "pulse_count:inst2|PULSE_COUNT[15]" register due to stuck clock or clock enable
Warning: Reduced register "pulse_count:inst2|PULSE_COUNT[15]" with stuck clock port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "PULSE_COUNT[15]" stuck at GND
    Warning: Pin "PULSE_COUNT[14]" stuck at GND
    Warning: Pin "PULSE_COUNT[13]" stuck at GND
    Warning: Pin "PULSE_COUNT[12]" stuck at GND
    Warning: Pin "PULSE_COUNT[11]" stuck at GND
    Warning: Pin "PULSE_COUNT[10]" stuck at GND
    Warning: Pin "PULSE_COUNT[9]" stuck at GND
    Warning: Pin "PULSE_COUNT[8]" stuck at GND
    Warning: Pin "PULSE_COUNT[7]" stuck at GND
    Warning: Pin "PULSE_COUNT[6]" stuck at GND
    Warning: Pin "PULSE_COUNT[5]" stuck at GND
    Warning: Pin "PULSE_COUNT[4]" stuck at GND
    Warning: Pin "PULSE_COUNT[3]" stuck at GND
    Warning: Pin "PULSE_COUNT[2]" stuck at GND
    Warning: Pin "PULSE_COUNT[1]" stuck at GND
    Warning: Pin "PULSE_COUNT[0]" stuck at GND
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "INA"
    Warning: No output dependent on input pin "CLR"
    Warning: No output dependent on input pin "INB"
    Warning: No output dependent on input pin "CLK"
Info: Implemented 20 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 62 warnings
    Info: Processing ended: Tue Jun 13 17:10:09 2006
    Info: Elapsed time: 00:00:04