speed_code.txt

FPGA光电编码器输入模块

 module speed_code(INA,INB,CLR,CLK,RESET,CE,PC_OUT);
   input INA,INB,CLR,CLK,RESET,CE;
   output PC_OUT;
   reg [15:0] PC_OUT;
   reg ENADD;
   reg DIRECTION;
   reg [15:0] PULSE_COUNT;
   
   
   
   
   
   
   
   
   
   
   F4 F4(INA,CLR,INB,CLK,F4_CLK,ENADD);
   pulse_count pusle_count(F4_CLK,RESET,.DIRECTION(ENADD),PULSE_COUNT);
   LATCH1 LATCH1(CLR,CE,PULSE_COUNT,PC_OUT);
   
endmodule