f4.fit.eqn

FPGA光电编码器输入模块

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--inst2 is inst2 at LCFF_X10_Y13_N9
inst2 = DFFEAS(inst1, GLOBAL(A1L2), GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--inst4 is inst4 at LCFF_X10_Y13_N11
inst4 = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L2), GLOBAL(A1L4),  ,  , INB,  ,  , VCC);


--inst5 is inst5 at LCFF_X10_Y13_N13
inst5 = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L2), GLOBAL(A1L4),  ,  , inst,  ,  , VCC);


--inst6 is inst6 at LCFF_X10_Y13_N23
inst6 = DFFEAS(A1L15, GLOBAL(A1L2), GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--inst is inst at LCFF_X10_Y13_N25
inst = DFFEAS(A1L19, GLOBAL(A1L2), GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--A1L16 is inst21~156 at LCCOMB_X10_Y13_N10
A1L16 = inst & (inst4 & !inst6 # !inst4 & (!inst5)) # !inst & (inst4 & (inst5) # !inst4 & inst6);


--A1L17 is inst22~190 at LCCOMB_X10_Y13_N12
A1L17 = inst & (inst4 & (!inst5) # !inst4 & inst6) # !inst & (inst4 & !inst6 # !inst4 & (inst5));


--inst26 is inst26 at LCCOMB_X10_Y13_N26
inst26 = !A1L16 & (A1L17 # inst26);


--inst1 is inst1 at LCCOMB_X10_Y13_N8
inst1 = inst5 & inst & (inst6 $ !inst4) # !inst5 & !inst & (inst6 $ !inst4);


--CLK is CLK at PIN_23
--operation mode is input

CLK = INPUT();


--CLR is CLR at PIN_24
--operation mode is input

CLR = INPUT();


--INB is INB at PIN_191
--operation mode is input

INB = INPUT();


--INA is INA at PIN_180
--operation mode is input

INA = INPUT();


--ENADD is ENADD at PIN_189
--operation mode is output

ENADD = OUTPUT(!inst26);


--F4_CLK is F4_CLK at PIN_198
--operation mode is output

F4_CLK = OUTPUT(inst2);





--A1L4 is CLR~clkctrl at CLKCTRL_G1
A1L4 = cycloneii_clkctrl(.INCLK[0] = CLR) WITH (clock_type = "Global Clock");


--A1L2 is CLK~clkctrl at CLKCTRL_G2
A1L2 = cycloneii_clkctrl(.INCLK[0] = CLK) WITH (clock_type = "Global Clock");


--A1L15 is inst6~feeder at LCCOMB_X10_Y13_N22
A1L15 = inst4;


--A1L19 is inst~feeder at LCCOMB_X10_Y13_N24
A1L19 = INA;