f4.tan.qmsg

FPGA光电编码器输入模块

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK ENADD inst 9.641 ns register " "Info: tco from clock \"CLK\" to destination pin \"ENADD\" through register \"inst\" is 9.641 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.803 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { CLK } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns inst 3 REG LCFF_X10_Y13_N25 4 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.520 ns" { CLK~clkctrl inst } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.534 ns + Longest register pin " "Info: + Longest register to pin delay is 6.534 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst 1 REG LCFF_X10_Y13_N25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { inst } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.484 ns) + CELL(0.650 ns) 1.134 ns inst22~190 2 COMB LCCOMB_X10_Y13_N12 2 " "Info: 2: + IC(0.484 ns) + CELL(0.650 ns) = 1.134 ns; Loc. = LCCOMB_X10_Y13_N12; Fanout = 2; COMB Node = 'inst22~190'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.134 ns" { inst inst22~190 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 200 712 776 280 "inst22" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.285 ns) 2.419 ns inst26 3 COMB LOOP LCCOMB_X10_Y13_N26 2 " "Info: 3: + IC(0.000 ns) + CELL(1.285 ns) = 2.419 ns; Loc. = LCCOMB_X10_Y13_N26; Fanout = 2; COMB LOOP Node = 'inst26'" { { "Info" "ITDB_PART_OF_SCC" "inst26 LCCOMB_X10_Y13_N26 " "Info: Loc. = LCCOMB_X10_Y13_N26; Node \"inst26\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { inst26 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { inst26 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 176 800 864 224 "inst26" "" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.285 ns" { inst22~190 inst26 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 176 800 864 224 "inst26" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(3.266 ns) 6.534 ns ENADD 4 PIN PIN_189 0 " "Info: 4: + IC(0.849 ns) + CELL(3.266 ns) = 6.534 ns; Loc. = PIN_189; Fanout = 0; PIN Node = 'ENADD'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "4.115 ns" { inst26 ENADD } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 208 928 1104 224 "ENADD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.201 ns ( 79.60 % ) " "Info: Total cell delay = 5.201 ns ( 79.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.333 ns ( 20.40 % ) " "Info: Total interconnect delay = 1.333 ns ( 20.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "6.534 ns" { inst inst22~190 inst26 ENADD } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.534 ns" { inst inst22~190 inst26 ENADD } { 0.000ns 0.484ns 0.000ns 0.849ns } { 0.000ns 0.650ns 1.285ns 3.266ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "6.534 ns" { inst inst22~190 inst26 ENADD } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.534 ns" { inst inst22~190 inst26 ENADD } { 0.000ns 0.484ns 0.000ns 0.849ns } { 0.000ns 0.650ns 1.285ns 3.266ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "inst4 INB CLK -4.035 ns register " "Info: th for register \"inst4\" (data pin = \"INB\", clock pin = \"CLK\") is -4.035 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.803 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { CLK } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns inst4 3 REG LCFF_X10_Y13_N11 4 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N11; Fanout = 4; REG Node = 'inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.520 ns" { CLK~clkctrl inst4 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst4 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.144 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns INB 1 PIN PIN_191 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_191; Fanout = 1; PIN Node = 'INB'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { INB } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 216 40 208 232 "INB" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.710 ns) + CELL(0.460 ns) 7.144 ns inst4 2 REG LCFF_X10_Y13_N11 4 " "Info: 2: + IC(5.710 ns) + CELL(0.460 ns) = 7.144 ns; Loc. = LCFF_X10_Y13_N11; Fanout = 4; REG Node = 'inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "6.170 ns" { INB inst4 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.434 ns ( 20.07 % ) " "Info: Total cell delay = 1.434 ns ( 20.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.710 ns ( 79.93 % ) " "Info: Total interconnect delay = 5.710 ns ( 79.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "7.144 ns" { INB inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.144 ns" { INB INB~combout inst4 } { 0.000ns 0.000ns 5.710ns } { 0.000ns 0.974ns 0.460ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst4 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "7.144 ns" { INB inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.144 ns" { INB INB~combout inst4 } { 0.000ns 0.000ns 5.710ns } { 0.000ns 0.974ns 0.460ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 17:00:49 2006 " "Info: Processing ended: Tue Jun 13 17:00:49 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}