f4.tan.qmsg

FPGA光电编码器输入模块

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "inst26 " "Info: Node \"inst26\"" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 176 800 864 224 "inst26" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 176 800 864 224 "inst26" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register inst5 inst2 340.02 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 340.02 MHz between source register \"inst5\" and destination register \"inst2\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.240 ns + Longest register register " "Info: + Longest register to register delay is 1.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst5 1 REG LCFF_X10_Y13_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N13; Fanout = 3; REG Node = 'inst5'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { inst5 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 384 448 160 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.651 ns) 1.132 ns inst1 2 COMB LCCOMB_X10_Y13_N8 1 " "Info: 2: + IC(0.481 ns) + CELL(0.651 ns) = 1.132 ns; Loc. = LCCOMB_X10_Y13_N8; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.132 ns" { inst5 inst1 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.240 ns inst2 3 REG LCFF_X10_Y13_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.240 ns; Loc. = LCFF_X10_Y13_N9; Fanout = 1; REG Node = 'inst2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.108 ns" { inst1 inst2 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { -8 944 1008 72 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 61.21 % ) " "Info: Total cell delay = 0.759 ns ( 61.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.481 ns ( 38.79 % ) " "Info: Total interconnect delay = 0.481 ns ( 38.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.240 ns" { inst5 inst1 inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.240 ns" { inst5 inst1 inst2 } { 0.000ns 0.481ns 0.000ns } { 0.000ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.803 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { CLK } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns inst2 3 REG LCFF_X10_Y13_N9 1 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N9; Fanout = 1; REG Node = 'inst2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.520 ns" { CLK~clkctrl inst2 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { -8 944 1008 72 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst2 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.803 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { CLK } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns inst5 3 REG LCFF_X10_Y13_N13 3 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N13; Fanout = 3; REG Node = 'inst5'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.520 ns" { CLK~clkctrl inst5 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 384 448 160 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst5 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst5 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst2 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst5 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst5 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 384 448 160 "inst5" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { -8 944 1008 72 "inst2" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.240 ns" { inst5 inst1 inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.240 ns" { inst5 inst1 inst2 } { 0.000ns 0.481ns 0.000ns } { 0.000ns 0.651ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst2 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst5 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst5 } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { inst2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { inst2 } {  } {  } } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { -8 944 1008 72 "inst2" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "inst INA CLK 4.749 ns register " "Info: tsu for register \"inst\" (data pin = \"INA\", clock pin = \"CLK\") is 4.749 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.592 ns + Longest pin register " "Info: + Longest pin to register delay is 7.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns INA 1 PIN PIN_180 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_180; Fanout = 1; PIN Node = 'INA'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { INA } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 96 40 208 112 "INA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.304 ns) + CELL(0.206 ns) 7.484 ns inst~feeder 2 COMB LCCOMB_X10_Y13_N24 1 " "Info: 2: + IC(6.304 ns) + CELL(0.206 ns) = 7.484 ns; Loc. = LCCOMB_X10_Y13_N24; Fanout = 1; COMB Node = 'inst~feeder'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "6.510 ns" { INA inst~feeder } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.592 ns inst 3 REG LCFF_X10_Y13_N25 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.592 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.108 ns" { inst~feeder inst } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.97 % ) " "Info: Total cell delay = 1.288 ns ( 16.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.304 ns ( 83.03 % ) " "Info: Total interconnect delay = 6.304 ns ( 83.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "7.592 ns" { INA inst~feeder inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.592 ns" { INA INA~combout inst~feeder inst } { 0.000ns 0.000ns 6.304ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.803 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "" { CLK } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 312 40 208 328 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns inst 3 REG LCFF_X10_Y13_N25 4 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "1.520 ns" { CLK~clkctrl inst } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/F4/F4.bdf" { { 80 264 328 160 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "7.592 ns" { INA inst~feeder inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.592 ns" { INA INA~combout inst~feeder inst } { 0.000ns 0.000ns 6.304ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "F4" "UNKNOWN" "V1" "D:/altera/fpga+dsp/F4/db/F4.quartus_db" { Floorplan "D:/altera/fpga+dsp/F4/" "" "2.803 ns" { CLK CLK~clkctrl inst } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.803 ns" { CLK CLK~combout CLK~clkctrl inst } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}